2019-03-29 14:12:17 +08:00
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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2018-11-01 18:02:22 +08:00
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From: Xinyun Liu <xinyun.liu@intel.com>
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Date: Wed, 19 Sep 2018 15:28:53 +0800
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2019-03-29 14:12:17 +08:00
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Subject: [PATCH] drm/i915/gvt: correct mask setting for CSFE_CHICKEN1
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2018-11-01 18:02:22 +08:00
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CSFE_CHICKEN1(0x20d4) needs access with mask. This is caught in AcrnGT
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conformance check test:
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[drm:intel_gvt_vgpu_conformance_check]
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*ERROR* gvt: vgpu1 unconformance mmio 0x20d4:0x40004,0x4
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Tracked-On: projectacrn/acrn-hypervisor#1459
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Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
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---
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drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
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2020-05-05 09:02:46 +08:00
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index e6c592f44..dc0a14729 100644
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2018-11-01 18:02:22 +08:00
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--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
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+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
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@@ -144,7 +144,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
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{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
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{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
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- {RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */
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+ {RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
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{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
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{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
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--
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2019-04-08 18:08:36 +08:00
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https://clearlinux.org
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2018-11-01 18:02:22 +08:00
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