2019-03-29 14:12:17 +08:00
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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2019-02-28 15:18:07 +08:00
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From: "He, Min" <min.he@intel.com>
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Date: Fri, 22 Feb 2019 02:23:55 +0000
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2019-03-29 14:12:17 +08:00
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Subject: [PATCH] drm/i915/gvt: add PIPEDSL to pvmmio trap list to read HW
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2019-02-28 15:18:07 +08:00
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PIPEDSL register for guest
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The PipeDSL register will be read in irq handler. But currently it
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is accessed based on write-protected mode after PVMMIO is enabled.
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This patch added PIPEDSL registers to the pvmmio trap list so that guest
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will be able to read the HW PIPEDSL registers. This patch can help to
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reduce the time consumption of vblank irq handler in guest.
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Change-Id: Ie9d2fa0125db9dadd5475fa8aeb036cde2adb90d
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Tracked-On: projectacrn/acrn-hypervisor#2597
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Signed-off-by: He, Min <min.he@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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Tracked-On: PKT-1750
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---
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drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
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1 file changed, 7 insertions(+)
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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2019-03-29 14:12:17 +08:00
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index 0297014..78c46e1 100644
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2019-02-28 15:18:07 +08:00
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -5642,6 +5642,9 @@ enum {
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#define PIPE_B_OFFSET 0x71000
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#define PIPE_C_OFFSET 0x72000
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#define CHV_PIPE_C_OFFSET 0x74000
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+
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+#define __PIPEBDSL 0x71000
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+#define __PIPECDSL 0x72000
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/*
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* There's actually no pipe EDP. Some pipe registers have
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* simply shifted from the pipe to the transcoder, while
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@@ -10681,6 +10684,10 @@ static inline bool in_mmio_read_trap_list(u32 reg)
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if (unlikely(reg == SBI_DATA.reg || reg == 0x6c060 || reg == 0x206c))
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return true;
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+ if (unlikely(reg == _PIPEADSL ||
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+ reg == __PIPEBDSL ||
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+ reg == __PIPECDSL))
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+ return true;
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return false;
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}
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--
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2019-03-29 14:12:17 +08:00
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2.21.0
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2019-02-28 15:18:07 +08:00
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