2019-03-29 14:12:17 +08:00
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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2018-10-11 02:06:46 +08:00
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From: Zhao Yakui <yakui.zhao@intel.com>
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Date: Fri, 14 Sep 2018 16:10:20 +0800
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2019-03-29 14:12:17 +08:00
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Subject: [PATCH] drm/i915: Use 64-bit write to optimize writing fence_reg
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2018-10-11 02:06:46 +08:00
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On VGPU scenario the read/write operation of fence_reg will be trapped
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by the GVT-g. Then gvt-g follows the HW spec to program the fence_reg.
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And the gvt-g takes care of updating the fence reg correctly for any trapped
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value of fence reg.
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So it is unnecessary to read/write fence reg several times. It is enough that
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the fence reg is written only value in 64-bit mode. This will help
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to reduce the redundant trap of fence_reg mmio operation.
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V1->V2: Add back the condition judgement of !pipelined
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Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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Reviewed-by: He Min <min.he@intel.com>
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---
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drivers/gpu/drm/i915/i915_gem_fence_reg.c | 15 ++++++++++++---
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1 file changed, 12 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
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2019-03-29 14:12:17 +08:00
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index d548ac0..317e376 100644
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2018-10-11 02:06:46 +08:00
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--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
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+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
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@@ -63,6 +63,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
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i915_reg_t fence_reg_lo, fence_reg_hi;
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int fence_pitch_shift;
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u64 val;
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+ struct drm_i915_private *dev_priv = fence->i915;
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if (INTEL_GEN(fence->i915) >= 6) {
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fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
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@@ -92,9 +93,17 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
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val |= I965_FENCE_REG_VALID;
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}
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- if (!pipelined) {
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- struct drm_i915_private *dev_priv = fence->i915;
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-
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+ if (intel_vgpu_active(dev_priv)) {
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+ /* Use the 64-bit RW to write fence reg on VGPU mode.
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+ * The GVT-g can trap the written val of VGPU to program the
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+ * fence reg. And the fence write in gvt-g follows the
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+ * sequence of off/read/double-write/read. This assures that
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+ * the fence reg is configured as expected.
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+ * At the same time the 64-bit op can help to reduce the num
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+ * of VGPU trap for the fence reg.
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+ */
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+ I915_WRITE64_FW(fence_reg_lo, val);
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+ } else if (!pipelined) {
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/* To w/a incoherency with non-atomic 64-bit register updates,
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* we split the 64-bit update into two 32-bit writes. In order
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* for a partial fence not to be evaluated between writes, we
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--
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2019-03-29 14:12:17 +08:00
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2.21.0
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2018-10-11 02:06:46 +08:00
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