2019-09-10 10:09:19 +08:00
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: qianmenx <qianx.meng@intel.com>
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Date: Thu, 9 May 2019 10:42:25 +0800
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Subject: [PATCH] media: intel-ipu4: update metadata info for x3a
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update metadata info for x3a
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- change crl_ox03a10_common.h
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add registers of frame counter, DCG exp, VS exp,
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HCG Dgain, LCG Dgain, VS Dgain,
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HCG Again, LCG Again, VS Again
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now frame counter can't work, the value always 0
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Change-Id: Ic7555778372eff8e06af416a858c8aa0faf54655
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Tracked-On: PKT-2588
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Tracked-On: #JIIAP-750
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Signed-off-by: qianmenx <qianx.meng@intel.com>
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Signed-off-by: Meng Wei <wei.meng@intel.com>
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---
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drivers/media/i2c/crlmodule/crl_ox03a10_common.h | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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diff --git a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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2020-10-27 02:14:06 +08:00
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index ceaed8f2466b..6f3fedfefec2 100644
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2019-09-10 10:09:19 +08:00
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--- a/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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+++ b/drivers/media/i2c/crlmodule/crl_ox03a10_common.h
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@@ -530,8 +530,15 @@ static struct crl_register_write_rep ox03a10_1920_1088_12DCG[] = {
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{ 0x460a, CRL_REG_LEN_08BIT, 0x0e },
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/* embedded data */
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{ 0x3208, CRL_REG_LEN_08BIT, 0x04 },
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- { 0x3800, CRL_REG_LEN_08BIT, 0x03 },
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- { 0x4800, CRL_REG_LEN_08BIT, 0x02 },
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+ { 0x483e, CRL_REG_LEN_08BIT, 0x02 },/* frame counter */
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+ { 0x3501, CRL_REG_LEN_08BIT, 0x02 },/* DCG exp */
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+ { 0x3581, CRL_REG_LEN_08BIT, 0x02 },/* VS exp */
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+ { 0x350a, CRL_REG_LEN_08BIT, 0x02 },/* HCG Dgain */
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+ { 0x354a, CRL_REG_LEN_08BIT, 0x02 },/* LCG Dgain */
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+ { 0x358a, CRL_REG_LEN_08BIT, 0x02 },/* VS Dgain */
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+ { 0x3508, CRL_REG_LEN_08BIT, 0x02 },/* HCG Again */
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+ { 0x3548, CRL_REG_LEN_08BIT, 0x02 },/* LCG Again */
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+ { 0x3588, CRL_REG_LEN_08BIT, 0x02 },/* VS Again */
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{ 0x3208, CRL_REG_LEN_08BIT, 0x14 },
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{ 0x3208, CRL_REG_LEN_08BIT, 0x05 },
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{ 0x5000, CRL_REG_LEN_08BIT, 0x10 },
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--
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https://clearlinux.org
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