clear-pkgs-linux-iot-lts2018/0592-drm-i915-gvt-Add-new-trace-point-to-output-per-domai.patch

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Brahim Abes <brahimx.abes@intel.com>
Date: Fri, 14 Sep 2018 16:10:18 +0800
Subject: [PATCH] drm/i915/gvt: Add new trace point to output per domain info

Added trace point "i915_gem_request_add_domain" that prints the following
extra fields per each packet:
        -is_shadow_ctx: Check for Dom0 or guest domains
        -hw_id: To check against i915_context_status's HW context id
        -vgt_id: The host or guests domain ID
        -pid: Process ID submitting the request

Change-Id: I3a71e1d5909260df5a07c98291ee9e908f698ea2
Signed-off-by: Brahim Abes <brahimx.abes@intel.com>
Reviewed-by: Singh, Satyeshwar <satyeshwar.singh@intel.com>
Reviewed-on:
Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
Reviewed-by: He, Min <min.he@intel.com>
Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
Tested-by: Dong, Eddie <eddie.dong@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 30 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_request.c |  1 +
 drivers/gpu/drm/i915/i915_trace.h   | 47 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h    |  5 +++
 4 files changed, 83 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4a1330a42a28..c8800a9a89fc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1943,6 +1943,36 @@ static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
 		   ring->space, ring->head, ring->tail, ring->emit);
 }
 
+bool is_shadow_context(struct i915_gem_context *ctx)
+{
+	if (ctx->name && !strncmp(ctx->name, "Shadow Context", 14))
+		return true;
+
+	return false;
+}
+
+int get_vgt_id(struct i915_gem_context *ctx)
+{
+	int vgt_id;
+
+	vgt_id = 0;
+
+	if (is_shadow_context(ctx))
+		sscanf(ctx->name, "Shadow Context %d", &vgt_id);
+
+	return vgt_id;
+}
+
+int get_pid_shadowed(struct i915_gem_context *ctx,
+		struct intel_engine_cs *engine)
+{
+	int pid, vgt_id;
+
+	sscanf(ctx->name, "Shadow Context %d", &vgt_id);
+	pid = intel_read_status_page(engine, I915_GEM_HWS_PID_INDEX + vgt_id);
+	return pid;
+}
+
 static void describe_ctx_ring_shadowed(struct seq_file *m,
 		struct i915_gem_context *ctx, struct intel_ring *ring,
 		struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 5c2c93cbab12..1bd2a7ef1885 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1054,6 +1054,7 @@ void i915_request_add(struct i915_request *request)
 
 	lockdep_assert_held(&request->i915->drm.struct_mutex);
 	trace_i915_request_add(request);
+	trace_i915_request_add_domain(request);
 
 	/*
 	 * Make sure that no request gazumped us - if it was allocated after
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index b50c6b829715..af592e3d09a9 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -679,6 +679,53 @@ DEFINE_EVENT(i915_request, i915_request_add,
 	    TP_ARGS(rq)
 );
 
+TRACE_EVENT(i915_multi_domains,
+	    TP_PROTO(struct i915_request *req),
+	    TP_ARGS(req),
+
+	    TP_STRUCT__entry(
+			     __field(u32, dev)
+			     __field(u32, ctx)
+			     __field(u32, ring)
+			     __field(u32, seqno)
+			     __field(u32, global)
+			     __field(int, prio_req)
+			     __field(int, prio_ctx)
+			     __field(bool, shadow_ctx)
+			     __field(u32, hw_id)
+			     __field(int, vgt_id)
+			     __field(u32, pid)
+			     ),
+
+	    TP_fast_assign(
+			   __entry->dev = req->i915->drm.primary->index;
+			   __entry->ring = req->engine->id;
+			   __entry->ctx = req->fence.context;
+			   __entry->seqno = req->fence.seqno;
+			   __entry->global = req->global_seqno;
+			   __entry->prio_req = req->sched.attr.priority;
+			   __entry->prio_ctx = req->sched.attr.priority;
+			   __entry->shadow_ctx = is_shadow_context(req->gem_context);
+			   __entry->hw_id = req->gem_context->hw_id;
+			   __entry->vgt_id = get_vgt_id(req->gem_context);
+			   __entry->pid = is_shadow_context(req->gem_context) ?
+				get_pid_shadowed(req->gem_context, req->engine) :
+				pid_nr(req->gem_context->pid);
+			   ),
+
+	    TP_printk("dev=%u, ring=%u, ctx=%u, seqno=%u, global=%u, "
+		      "priority=%d (%d), is_shadow_ctx=%u, hw_id=%u, "
+		      "vgt_id=%u, pid=%u", __entry->dev,  __entry->ring,
+		      __entry->ctx, __entry->seqno, __entry->global,
+		      __entry->prio_req, __entry->prio_ctx, __entry->shadow_ctx,
+		      __entry->hw_id, __entry->vgt_id, __entry->pid)
+);
+
+DEFINE_EVENT(i915_multi_domains, i915_request_add_domain,
+	    TP_PROTO(struct i915_request *req),
+	    TP_ARGS(req)
+);
+
 #if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS)
 DEFINE_EVENT(i915_request, i915_request_submit,
 	     TP_PROTO(struct i915_request *rq),
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1c96e927e91a..1beb040b846f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1394,6 +1394,11 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 	return dev_priv->runtime_pm.irqs_enabled;
 }
 
+bool is_shadow_context(struct i915_gem_context *ctx);
+int get_vgt_id(struct i915_gem_context *ctx);
+int get_pid_shadowed(struct i915_gem_context *ctx,
+		      struct intel_engine_cs *engine);
+
 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask);
-- 
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