2019-03-29 14:12:17 +08:00
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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2018-10-16 02:05:43 +08:00
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From: Hardik T Shah <hardik.t.shah@intel.com>
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Date: Mon, 25 Apr 2016 13:39:37 +0530
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2019-03-29 14:12:17 +08:00
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Subject: [PATCH] SDW:Intel: Fix hardcoding for SVFPGA codec.
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2018-10-16 02:05:43 +08:00
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SVFPGA codec requires special handling as its not modelled
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as MIPI defined SoundWire Slave. This is used for testing PDM
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mode on master. So hardcode clock setting for only SVFPGA codec.
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This patch doesnt need to be upstream.
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Change-Id: I723b1258d2186783a16ef7a60934a6ce7d6ffacc
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Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
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Reviewed-on:
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---
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drivers/sdw/sdw_cnl.c | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/drivers/sdw/sdw_cnl.c b/drivers/sdw/sdw_cnl.c
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2020-10-27 02:14:06 +08:00
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index 3f3317a6707a..9686aa2f9caf 100644
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2018-10-16 02:05:43 +08:00
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--- a/drivers/sdw/sdw_cnl.c
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+++ b/drivers/sdw/sdw_cnl.c
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@@ -1097,7 +1097,11 @@ static int cnl_sdw_set_clock_freq(struct sdw_master *mstr,
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/* TODO: Retrieve divider value or get value directly from calling
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* function
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*/
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+#ifdef CONFIG_SND_SOC_SVFPGA
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+ int divider = ((9600000 * 2/cur_clk_freq) - 1);
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+#else
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int divider = ((9600000/cur_clk_freq) - 1);
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+#endif
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if (bank) {
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mcp_clockctrl_offset = SDW_CNL_MCP_CLOCKCTRL1;
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--
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2019-04-08 18:08:36 +08:00
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https://clearlinux.org
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2018-10-16 02:05:43 +08:00
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