78 lines
2.7 KiB
Diff
78 lines
2.7 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Junming Liu <junming.liu@intel.com>
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Date: Fri, 30 Aug 2019 18:10:47 +0000
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Subject: [PATCH] drm/i915/gvt: addressed guest GPU hang with HWS index mode
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with the introduce of "switch to use HWS indices rather than address",
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guest GPU hang observed when running workloads which will update the
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seqno to the real HW HWSP, not vitural GPU HWSP and then cause GPU hang.
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this patch is to revoke index mode in PIPE_CTRL and MI_FLUSH_DW and
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patch guest GPU HWSP address value to these commands.
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Tracked-On: projectacrn/acrn-hypervisor#3630
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Signed-off-by: Junming Liu <junming.liu@intel.com>
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Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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---
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drivers/gpu/drm/i915/gvt/cmd_parser.c | 20 ++++++++++++++++++++
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1 file changed, 20 insertions(+)
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diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
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index 150ba0f07a5d..3db229220036 100644
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--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
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+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
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@@ -1115,6 +1115,7 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s)
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bool index_mode = false;
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unsigned int post_sync;
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int ret = 0;
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+ u32 hws_pga, val;
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post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
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@@ -1138,6 +1139,15 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s)
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index_mode = true;
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ret |= cmd_address_audit(s, gma, sizeof(u64),
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index_mode);
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+ if (ret)
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+ return ret;
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+ if (index_mode) {
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+ hws_pga = s->vgpu->hws_pga[s->ring_id];
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+ gma = hws_pga + gma;
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+ patch_value(s, cmd_ptr(s, 2), gma);
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+ val = cmd_val(s, 1) & (~(1 << 21));
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+ patch_value(s, cmd_ptr(s, 1), val);
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+ }
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}
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}
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}
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@@ -1607,6 +1617,7 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
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unsigned long gma;
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bool index_mode = false;
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int ret = 0;
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+ u32 hws_pga, val;
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/* Check post-sync and ppgtt bit */
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if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
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@@ -1617,6 +1628,15 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
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if (cmd_val(s, 0) & (1 << 21))
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index_mode = true;
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ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
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+ if (ret)
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+ return ret;
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+ if (index_mode) {
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+ hws_pga = s->vgpu->hws_pga[s->ring_id];
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+ gma = hws_pga + gma;
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+ patch_value(s, cmd_ptr(s, 1), gma);
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+ val = cmd_val(s, 0) & (~(1 << 21));
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+ patch_value(s, cmd_ptr(s, 0), val);
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+ }
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}
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/* Check notify bit */
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if ((cmd_val(s, 0) & (1 << 8)))
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--
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https://clearlinux.org
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