2019-03-29 14:12:17 +08:00
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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2018-10-11 02:06:46 +08:00
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From: Min He <min.he@intel.com>
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Date: Fri, 14 Sep 2018 16:10:22 +0800
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2019-03-29 14:12:17 +08:00
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Subject: [PATCH] drm/i915: to limit the supported modifiers for plane
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2018-10-11 02:06:46 +08:00
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restriction
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In GVT-g environment, to ensure all the OS's have enough DDB to
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display, GVT-g will statically allocate all the DDBs for all the
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planes on all the pipes.
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However, when SOS or UOS wants to use Y/Yf tiled modifier, the watermark
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required will exceed the DDBs allocated by GVT-g, thus causes some
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display issues.
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So in this patch, we removed the supports of the Y/Yf tiled modifiers
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for both SOS and UOS when plane restriction is enabled. And a consequence
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is that the RBC will be disabled since _CCS modifiers will no longer be
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supported.
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Tracked-on: https://github.com/projectacrn/acrn-hypervisor/issues/1193
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Signed-off-by: Min He <min.he@intel.com>
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Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
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Reviewed-by: Fei Jiang <fei.jiang@intel.com>
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2018-10-20 01:05:20 +08:00
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V2: revert commit 01ba86, cd00ba and limited to gvt_active or vgpu_active
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Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
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Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
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2018-10-11 02:06:46 +08:00
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---
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2018-10-20 01:05:20 +08:00
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drivers/gpu/drm/i915/intel_display.c | 6 ++++++
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drivers/gpu/drm/i915/intel_sprite.c | 3 +++
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2 files changed, 9 insertions(+)
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2018-10-11 02:06:46 +08:00
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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2020-10-27 02:14:06 +08:00
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index da537980a936..72eacb50442e 100644
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2018-10-11 02:06:46 +08:00
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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2019-09-19 15:09:25 +08:00
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@@ -13786,6 +13786,9 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
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2018-10-20 01:05:20 +08:00
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else
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modifiers = skl_format_modifiers_noccs;
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2018-10-11 02:06:46 +08:00
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2018-10-20 01:05:20 +08:00
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+ if (intel_gvt_active(dev_priv) || intel_vgpu_active(dev_priv))
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+ modifiers = i9xx_format_modifiers;
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+
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2018-10-11 02:06:46 +08:00
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primary->update_plane = skl_update_plane;
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primary->disable_plane = skl_disable_plane;
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2018-10-20 01:05:20 +08:00
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primary->get_hw_state = skl_plane_get_hw_state;
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2019-09-19 15:09:25 +08:00
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@@ -13947,6 +13950,9 @@ intel_skl_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe,
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2018-10-20 01:05:20 +08:00
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else
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modifiers = skl_format_modifiers_noccs;
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+ if (intel_gvt_active(dev_priv) || intel_vgpu_active(dev_priv))
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+ modifiers = i9xx_format_modifiers;
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+
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num_formats = ARRAY_SIZE(skl_primary_formats);
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/*
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2018-10-11 02:06:46 +08:00
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diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
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2020-10-27 02:14:06 +08:00
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index e10a64a6265c..7b8e2c7c9f8d 100644
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2018-10-11 02:06:46 +08:00
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--- a/drivers/gpu/drm/i915/intel_sprite.c
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+++ b/drivers/gpu/drm/i915/intel_sprite.c
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2018-10-20 01:05:20 +08:00
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@@ -1629,6 +1629,9 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
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else
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modifiers = skl_plane_format_modifiers_noccs;
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2018-10-11 02:06:46 +08:00
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2018-10-20 01:05:20 +08:00
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+ if (intel_gvt_active(dev_priv) || intel_vgpu_active(dev_priv))
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+ modifiers = i9xx_plane_format_modifiers;
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+
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2018-10-11 02:06:46 +08:00
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plane_funcs = &skl_plane_funcs;
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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2018-10-20 01:05:20 +08:00
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intel_plane->can_scale = false;
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2018-10-11 02:06:46 +08:00
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--
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2019-04-08 18:08:36 +08:00
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https://clearlinux.org
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2018-10-11 02:06:46 +08:00
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