2019-03-29 14:12:17 +08:00
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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2018-10-11 02:06:46 +08:00
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From: Fei Jiang <fei.jiang@intel.com>
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Date: Tue, 27 Mar 2018 22:59:22 +0800
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2019-03-29 14:12:17 +08:00
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Subject: [PATCH] drm/i915/gvt: unset DDI_BUF_CTL_ENABLE during port emulation
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reset
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2018-10-11 02:06:46 +08:00
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HDMI port enabling will assert port status, if it's already set during
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reset stage, i915 will pop up warning message. Unset those bits to avoid
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such warning message.
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Signed-off-by: Fei Jiang <fei.jiang@intel.com>
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Change-Id: Ic8c738baa472d7f1086081cb1b634670327aae97
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---
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drivers/gpu/drm/i915/gvt/display.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
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2020-10-27 02:14:06 +08:00
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index 39b255985cd8..9a41756c7df3 100644
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2018-10-11 02:06:46 +08:00
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--- a/drivers/gpu/drm/i915/gvt/display.c
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+++ b/drivers/gpu/drm/i915/gvt/display.c
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2020-06-21 05:57:46 +08:00
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@@ -255,7 +255,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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2018-10-11 02:06:46 +08:00
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vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
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PORT_CLK_SEL_LCPLL_810;
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}
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- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
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+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_CTL_ENABLE;
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vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
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vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
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}
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2020-06-21 05:57:46 +08:00
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@@ -281,7 +281,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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2018-10-11 02:06:46 +08:00
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vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
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PORT_CLK_SEL_LCPLL_810;
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}
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- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
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+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_CTL_ENABLE;
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vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
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vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
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}
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2020-06-21 05:57:46 +08:00
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@@ -307,7 +307,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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2018-10-11 02:06:46 +08:00
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vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
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PORT_CLK_SEL_LCPLL_810;
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}
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- vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
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+ vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_CTL_ENABLE;
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vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
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vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
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}
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--
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2019-04-08 18:08:36 +08:00
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https://clearlinux.org
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2018-10-11 02:06:46 +08:00
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