2019-03-29 14:12:17 +08:00
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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2018-10-11 02:06:46 +08:00
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From: Satyeshwar Singh <satyeshwar.singh@intel.com>
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Date: Wed, 13 Sep 2017 17:29:57 -0700
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2019-03-29 14:12:17 +08:00
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Subject: [PATCH] drm/i915/gvt: Raise a uevent when Dom 0 is ready for Dom U
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2018-10-11 02:06:46 +08:00
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HV vendors want to know when Dom 0 is ready to start a Dom U
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because they want to start Dom U as early as possible. This
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feature informs XenGT module as soon as Dom 0 is ready. In our
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example, we raise a uevent from XenGT module but the HV vendors
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are free to change the module to do any custom action that they
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want.
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Change-Id: Ibfdaca65002825e14e15527c386db00f59b372e5
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Signed-off-by: Satyeshwar Singh <satyeshwar.singh@intel.com>
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Reviewed-by: He, Min <min.he@intel.com>
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2018-10-16 02:05:43 +08:00
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Reviewed-on:
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2018-10-11 02:06:46 +08:00
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Reviewed-by: Jiang, Fei <fei.jiang@intel.com>
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Reviewed-by: Dong, Eddie <eddie.dong@intel.com>
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Tested-by: Dong, Eddie <eddie.dong@intel.com>
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---
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drivers/gpu/drm/i915/gvt/gvt.c | 8 ++++++++
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drivers/gpu/drm/i915/gvt/gvt.h | 1 +
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drivers/gpu/drm/i915/gvt/hypercall.h | 1 +
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drivers/gpu/drm/i915/gvt/mpt.h | 8 ++++++++
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drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
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5 files changed, 31 insertions(+)
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
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2021-06-16 23:22:13 +08:00
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index 383281a26a2f..8091582adbb5 100644
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2018-10-11 02:06:46 +08:00
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--- a/drivers/gpu/drm/i915/gvt/gvt.c
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+++ b/drivers/gpu/drm/i915/gvt/gvt.c
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@@ -511,6 +511,14 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
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return ret;
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}
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+int gvt_dom0_ready(struct drm_i915_private *dev_priv)
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+{
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+ if (!intel_gvt_active(dev_priv))
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+ return 0;
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+
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+ return intel_gvt_hypervisor_dom0_ready();
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+}
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+
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#if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
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MODULE_SOFTDEP("pre: kvmgt");
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#endif
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diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
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2020-10-27 02:14:06 +08:00
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index 47ed1789ea28..9c291924c1d0 100644
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2018-10-11 02:06:46 +08:00
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--- a/drivers/gpu/drm/i915/gvt/gvt.h
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+++ b/drivers/gpu/drm/i915/gvt/gvt.h
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@@ -592,6 +592,7 @@ struct intel_gvt_ops {
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unsigned int);
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};
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+int gvt_dom0_ready(struct drm_i915_private *dev_priv);
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enum {
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GVT_FAILSAFE_UNSUPPORTED_GUEST,
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diff --git a/drivers/gpu/drm/i915/gvt/hypercall.h b/drivers/gpu/drm/i915/gvt/hypercall.h
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2020-10-27 02:14:06 +08:00
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index 5af11cf1b482..f14cff32ae2f 100644
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2018-10-11 02:06:46 +08:00
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--- a/drivers/gpu/drm/i915/gvt/hypercall.h
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+++ b/drivers/gpu/drm/i915/gvt/hypercall.h
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@@ -64,6 +64,7 @@ struct intel_gvt_mpt {
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int (*get_vfio_device)(void *vgpu);
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void (*put_vfio_device)(void *vgpu);
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bool (*is_valid_gfn)(unsigned long handle, unsigned long gfn);
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+ int (*dom0_ready)(void);
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};
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extern struct intel_gvt_mpt xengt_mpt;
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diff --git a/drivers/gpu/drm/i915/gvt/mpt.h b/drivers/gpu/drm/i915/gvt/mpt.h
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2020-10-27 02:14:06 +08:00
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index 67f19992b226..feed7adb6fde 100644
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2018-10-11 02:06:46 +08:00
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--- a/drivers/gpu/drm/i915/gvt/mpt.h
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+++ b/drivers/gpu/drm/i915/gvt/mpt.h
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@@ -362,4 +362,12 @@ static inline bool intel_gvt_hypervisor_is_valid_gfn(
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return intel_gvt_host.mpt->is_valid_gfn(vgpu->handle, gfn);
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}
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+static inline int intel_gvt_hypervisor_dom0_ready(void)
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+{
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+ if (!intel_gvt_host.mpt->dom0_ready)
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+ return 0;
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+
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+ return intel_gvt_host.mpt->dom0_ready();
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+}
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+
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#endif /* _GVT_MPT_H_ */
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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2020-10-27 02:14:06 +08:00
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index 5c71bf36472b..9e9a8c448b4d 100644
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2018-10-11 02:06:46 +08:00
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -49,6 +49,10 @@
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#include <linux/dma_remapping.h>
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#include <linux/reservation.h>
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+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
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+#include "gvt.h"
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+#endif
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+
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/* Primary plane formats for gen <= 3 */
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static const uint32_t i8xx_primary_formats[] = {
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DRM_FORMAT_C8,
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2019-09-19 15:09:25 +08:00
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@@ -14349,6 +14353,15 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
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2018-10-11 02:06:46 +08:00
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intel_encoder_clones(encoder);
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}
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+#if IS_ENABLED(CONFIG_DRM_I915_GVT)
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+ /*
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+ * Encoders have been initialized. If we are in VGT mode,
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+ * let's inform the HV that it can start Dom U as Dom 0
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+ * is ready to accept new Dom Us.
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+ */
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+ gvt_dom0_ready(dev_priv);
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+#endif
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+
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intel_init_pch_refclk(dev_priv);
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drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
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--
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2019-04-08 18:08:36 +08:00
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https://clearlinux.org
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2018-10-11 02:06:46 +08:00
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