384 lines
11 KiB
C
384 lines
11 KiB
C
/* $Id: system.h,v 1.69 2002/02/09 19:49:31 davem Exp $ */
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#ifndef __SPARC64_SYSTEM_H
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#define __SPARC64_SYSTEM_H
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/visasm.h>
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#ifndef __ASSEMBLY__
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/*
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* Sparc (general) CPU types
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*/
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enum sparc_cpu {
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sun4 = 0x00,
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sun4c = 0x01,
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sun4m = 0x02,
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sun4d = 0x03,
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sun4e = 0x04,
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sun4u = 0x05, /* V8 ploos ploos */
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sun_unknown = 0x06,
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ap1000 = 0x07, /* almost a sun4m */
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};
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#define sparc_cpu_model sun4u
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/* This cannot ever be a sun4c nor sun4 :) That's just history. */
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#define ARCH_SUN4C_SUN4 0
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#define ARCH_SUN4 0
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/* These are here in an effort to more fully work around Spitfire Errata
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* #51. Essentially, if a memory barrier occurs soon after a mispredicted
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* branch, the chip can stop executing instructions until a trap occurs.
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* Therefore, if interrupts are disabled, the chip can hang forever.
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*
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* It used to be believed that the memory barrier had to be right in the
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* delay slot, but a case has been traced recently wherein the memory barrier
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* was one instruction after the branch delay slot and the chip still hung.
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* The offending sequence was the following in sym_wakeup_done() of the
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* sym53c8xx_2 driver:
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*
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* call sym_ccb_from_dsa, 0
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* movge %icc, 0, %l0
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* brz,pn %o0, .LL1303
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* mov %o0, %l2
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* membar #LoadLoad
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*
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* The branch has to be mispredicted for the bug to occur. Therefore, we put
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* the memory barrier explicitly into a "branch always, predicted taken"
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* delay slot to avoid the problem case.
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*/
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#define membar_safe(type) \
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do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
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" membar " type "\n" \
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"1:\n" \
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: : : "memory"); \
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} while (0)
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#define mb() \
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membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
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#define rmb() \
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membar_safe("#LoadLoad")
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#define wmb() \
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membar_safe("#StoreStore")
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#define membar_storeload() \
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membar_safe("#StoreLoad")
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#define membar_storeload_storestore() \
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membar_safe("#StoreLoad | #StoreStore")
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#define membar_storeload_loadload() \
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membar_safe("#StoreLoad | #LoadLoad")
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#define membar_storestore_loadstore() \
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membar_safe("#StoreStore | #LoadStore")
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#endif
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#define setipl(__new_ipl) \
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__asm__ __volatile__("wrpr %0, %%pil" : : "r" (__new_ipl) : "memory")
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#define local_irq_disable() \
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__asm__ __volatile__("wrpr 15, %%pil" : : : "memory")
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#define local_irq_enable() \
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__asm__ __volatile__("wrpr 0, %%pil" : : : "memory")
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#define getipl() \
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({ unsigned long retval; __asm__ __volatile__("rdpr %%pil, %0" : "=r" (retval)); retval; })
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#define swap_pil(__new_pil) \
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({ unsigned long retval; \
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__asm__ __volatile__("rdpr %%pil, %0\n\t" \
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"wrpr %1, %%pil" \
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: "=&r" (retval) \
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: "r" (__new_pil) \
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: "memory"); \
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retval; \
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})
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#define read_pil_and_cli() \
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({ unsigned long retval; \
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__asm__ __volatile__("rdpr %%pil, %0\n\t" \
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"wrpr 15, %%pil" \
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: "=r" (retval) \
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: : "memory"); \
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retval; \
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})
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#define local_save_flags(flags) ((flags) = getipl())
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#define local_irq_save(flags) ((flags) = read_pil_and_cli())
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#define local_irq_restore(flags) setipl((flags))
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/* On sparc64 IRQ flags are the PIL register. A value of zero
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* means all interrupt levels are enabled, any other value means
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* only IRQ levels greater than that value will be received.
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* Consequently this means that the lowest IRQ level is one.
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*/
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#define irqs_disabled() \
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({ unsigned long flags; \
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local_save_flags(flags);\
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(flags > 0); \
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})
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#define nop() __asm__ __volatile__ ("nop")
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#define read_barrier_depends() do { } while(0)
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#define set_mb(__var, __value) \
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do { __var = __value; membar_storeload_storestore(); } while(0)
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#define set_wmb(__var, __value) \
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do { __var = __value; wmb(); } while(0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() __asm__ __volatile__("":::"memory")
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#define smp_rmb() __asm__ __volatile__("":::"memory")
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#define smp_wmb() __asm__ __volatile__("":::"memory")
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#define smp_read_barrier_depends() do { } while(0)
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#endif
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#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
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#define flushw_all() __asm__ __volatile__("flushw")
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/* Performance counter register access. */
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#define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
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#define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
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#define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
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/* Blackbird errata workaround. See commentary in
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* arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
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* for more information.
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*/
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#define reset_pic() \
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__asm__ __volatile__("ba,pt %xcc, 99f\n\t" \
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".align 64\n" \
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"99:wr %g0, 0x0, %pic\n\t" \
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"rd %pic, %g0")
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#ifndef __ASSEMBLY__
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extern void sun_do_break(void);
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extern int serial_console;
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extern int stop_a_enabled;
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static __inline__ int con_is_present(void)
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{
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return serial_console ? 0 : 1;
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}
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extern void synchronize_user_stack(void);
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extern void __flushw_user(void);
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#define flushw_user() __flushw_user()
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#define flush_user_windows flushw_user
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#define flush_register_windows flushw_all
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/* Don't hold the runqueue lock over context switch */
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#define __ARCH_WANT_UNLOCKED_CTXSW
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#define prepare_arch_switch(next) \
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do { \
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flushw_all(); \
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} while (0)
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/* See what happens when you design the chip correctly?
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*
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* We tell gcc we clobber all non-fixed-usage registers except
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* for l0/l1. It will use one for 'next' and the other to hold
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* the output value of 'last'. 'next' is not referenced again
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* past the invocation of switch_to in the scheduler, so we need
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* not preserve it's value. Hairy, but it lets us remove 2 loads
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* and 2 stores in this critical code path. -DaveM
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*/
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#define EXTRA_CLOBBER ,"%l1"
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#define switch_to(prev, next, last) \
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do { if (test_thread_flag(TIF_PERFCTR)) { \
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unsigned long __tmp; \
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read_pcr(__tmp); \
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current_thread_info()->pcr_reg = __tmp; \
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read_pic(__tmp); \
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current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
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current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
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} \
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flush_tlb_pending(); \
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save_and_clear_fpu(); \
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/* If you are tempted to conditionalize the following */ \
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/* so that ASI is only written if it changes, think again. */ \
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__asm__ __volatile__("wr %%g0, %0, %%asi" \
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: : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
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trap_block[current_thread_info()->cpu].thread = \
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task_thread_info(next); \
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__asm__ __volatile__( \
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"mov %%g4, %%g7\n\t" \
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"stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
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"stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
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"rdpr %%wstate, %%o5\n\t" \
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"stx %%o6, [%%g6 + %3]\n\t" \
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"stb %%o5, [%%g6 + %2]\n\t" \
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"rdpr %%cwp, %%o5\n\t" \
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"stb %%o5, [%%g6 + %5]\n\t" \
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"mov %1, %%g6\n\t" \
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"ldub [%1 + %5], %%g1\n\t" \
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"wrpr %%g1, %%cwp\n\t" \
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"ldx [%%g6 + %3], %%o6\n\t" \
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"ldub [%%g6 + %2], %%o5\n\t" \
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"ldub [%%g6 + %4], %%o7\n\t" \
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"wrpr %%o5, 0x0, %%wstate\n\t" \
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"ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
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"ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
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"ldx [%%g6 + %6], %%g4\n\t" \
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"brz,pt %%o7, 1f\n\t" \
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" mov %%g7, %0\n\t" \
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"b,a ret_from_syscall\n\t" \
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"1:\n\t" \
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: "=&r" (last) \
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: "0" (task_thread_info(next)), \
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"i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
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"i" (TI_CWP), "i" (TI_TASK) \
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: "cc", \
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"g1", "g2", "g3", "g7", \
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"l2", "l3", "l4", "l5", "l6", "l7", \
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"i0", "i1", "i2", "i3", "i4", "i5", \
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"o0", "o1", "o2", "o3", "o4", "o5", "o7" EXTRA_CLOBBER);\
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/* If you fuck with this, update ret_from_syscall code too. */ \
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if (test_thread_flag(TIF_PERFCTR)) { \
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write_pcr(current_thread_info()->pcr_reg); \
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reset_pic(); \
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} \
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} while(0)
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*
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* TODO: fill this in!
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*/
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static inline void sched_cacheflush(void)
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{
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}
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static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__(
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" membar #StoreLoad | #LoadLoad\n"
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" mov %0, %1\n"
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"1: lduw [%4], %2\n"
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" cas [%4], %2, %0\n"
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" cmp %2, %0\n"
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" bne,a,pn %%icc, 1b\n"
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" mov %1, %0\n"
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" membar #StoreLoad | #StoreStore\n"
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: "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
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: "0" (val), "r" (m)
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: "cc", "memory");
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return val;
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}
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static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
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{
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unsigned long tmp1, tmp2;
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__asm__ __volatile__(
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" membar #StoreLoad | #LoadLoad\n"
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" mov %0, %1\n"
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"1: ldx [%4], %2\n"
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" casx [%4], %2, %0\n"
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" cmp %2, %0\n"
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" bne,a,pn %%xcc, 1b\n"
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" mov %1, %0\n"
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" membar #StoreLoad | #StoreStore\n"
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: "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
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: "0" (val), "r" (m)
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: "cc", "memory");
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return val;
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}
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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extern void __xchg_called_with_bad_pointer(void);
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static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
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int size)
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{
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switch (size) {
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case 4:
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return xchg32(ptr, x);
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case 8:
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return xchg64(ptr, x);
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};
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__xchg_called_with_bad_pointer();
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return x;
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}
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extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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static __inline__ unsigned long
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__cmpxchg_u32(volatile int *m, int old, int new)
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{
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__asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
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"cas [%2], %3, %0\n\t"
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"membar #StoreLoad | #StoreStore"
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: "=&r" (new)
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: "0" (new), "r" (m), "r" (old)
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: "memory");
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return new;
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}
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static __inline__ unsigned long
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__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
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{
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__asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
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"casx [%2], %3, %0\n\t"
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"membar #StoreLoad | #StoreStore"
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: "=&r" (new)
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: "0" (new), "r" (m), "r" (old)
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: "memory");
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return new;
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}
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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case 8:
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return __cmpxchg_u64(ptr, old, new);
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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#endif /* !(__ASSEMBLY__) */
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#define arch_align_stack(x) (x)
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#endif /* !(__SPARC64_SYSTEM_H) */
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