364 lines
14 KiB
C
364 lines
14 KiB
C
#ifndef __HEAD_BOOKE_H__
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#define __HEAD_BOOKE_H__
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/*
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* Macros used for common Book-e exception handling
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*/
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#define SET_IVOR(vector_number, vector_label) \
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li r26,vector_label@l; \
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mtspr SPRN_IVOR##vector_number,r26; \
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sync
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#define NORMAL_EXCEPTION_PROLOG \
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mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
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mtspr SPRN_SPRG1,r11; \
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mtspr SPRN_SPRG4W,r1; \
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mfcr r10; /* save CR in r10 for now */\
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mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
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andi. r11,r11,MSR_PR; \
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beq 1f; \
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mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\
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lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
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addi r1,r1,THREAD_SIZE; \
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1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
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mr r11,r1; \
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stw r10,_CCR(r11); /* save various registers */\
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stw r12,GPR12(r11); \
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stw r9,GPR9(r11); \
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mfspr r10,SPRN_SPRG0; \
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stw r10,GPR10(r11); \
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mfspr r12,SPRN_SPRG1; \
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stw r12,GPR11(r11); \
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mflr r10; \
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stw r10,_LINK(r11); \
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mfspr r10,SPRN_SPRG4R; \
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mfspr r12,SPRN_SRR0; \
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stw r10,GPR1(r11); \
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mfspr r9,SPRN_SRR1; \
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stw r10,0(r11); \
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rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
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stw r0,GPR0(r11); \
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SAVE_4GPRS(3, r11); \
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SAVE_2GPRS(7, r11)
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/* To handle the additional exception priority levels on 40x and Book-E
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* processors we allocate a 4k stack per additional priority level. The various
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* head_xxx.S files allocate space (exception_stack_top) for each priority's
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* stack times the number of CPUs
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*
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* On 40x critical is the only additional level
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* On 44x/e500 we have critical and machine check
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* On e200 we have critical and debug (machine check occurs via critical)
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*
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* Additionally we reserve a SPRG for each priority level so we can free up a
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* GPR to use as the base for indirect access to the exception stacks. This
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* is necessary since the MMU is always on, for Book-E parts, and the stacks
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* are offset from KERNELBASE.
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*
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*/
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#define BOOKE_EXCEPTION_STACK_SIZE (8192)
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/* CRIT_SPRG only used in critical exception handling */
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#define CRIT_SPRG SPRN_SPRG2
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/* MCHECK_SPRG only used in machine check exception handling */
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#define MCHECK_SPRG SPRN_SPRG6W
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#define MCHECK_STACK_TOP (exception_stack_top - 4096)
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#define CRIT_STACK_TOP (exception_stack_top)
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/* only on e200 for now */
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#define DEBUG_STACK_TOP (exception_stack_top - 4096)
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#define DEBUG_SPRG SPRN_SPRG6W
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#ifdef CONFIG_SMP
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#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
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mfspr r8,SPRN_PIR; \
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mulli r8,r8,BOOKE_EXCEPTION_STACK_SIZE; \
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neg r8,r8; \
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addis r8,r8,level##_STACK_TOP@ha; \
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addi r8,r8,level##_STACK_TOP@l
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#else
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#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
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lis r8,level##_STACK_TOP@h; \
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ori r8,r8,level##_STACK_TOP@l
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#endif
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/*
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* Exception prolog for critical/machine check exceptions. This is a
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* little different from the normal exception prolog above since a
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* critical/machine check exception can potentially occur at any point
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* during normal exception processing. Thus we cannot use the same SPRG
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* registers as the normal prolog above. Instead we use a portion of the
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* critical/machine check exception stack at low physical addresses.
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*/
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#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
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mtspr exc_level##_SPRG,r8; \
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BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
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stw r10,GPR10-INT_FRAME_SIZE(r8); \
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stw r11,GPR11-INT_FRAME_SIZE(r8); \
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mfcr r10; /* save CR in r10 for now */\
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mfspr r11,exc_level_srr1; /* check whether user or kernel */\
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andi. r11,r11,MSR_PR; \
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mr r11,r8; \
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mfspr r8,exc_level##_SPRG; \
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beq 1f; \
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/* COMING FROM USER MODE */ \
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mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\
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lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
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addi r11,r11,THREAD_SIZE; \
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1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\
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stw r10,_CCR(r11); /* save various registers */\
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stw r12,GPR12(r11); \
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stw r9,GPR9(r11); \
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mflr r10; \
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stw r10,_LINK(r11); \
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mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
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stw r12,_DEAR(r11); /* since they may have had stuff */\
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mfspr r9,SPRN_ESR; /* in them at the point where the */\
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stw r9,_ESR(r11); /* exception was taken */\
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mfspr r12,exc_level_srr0; \
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stw r1,GPR1(r11); \
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mfspr r9,exc_level_srr1; \
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stw r1,0(r11); \
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mr r1,r11; \
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rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
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stw r0,GPR0(r11); \
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SAVE_4GPRS(3, r11); \
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SAVE_2GPRS(7, r11)
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#define CRITICAL_EXCEPTION_PROLOG \
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EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
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#define DEBUG_EXCEPTION_PROLOG \
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EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
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#define MCHECK_EXCEPTION_PROLOG \
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EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)
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/*
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* Exception vectors.
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*/
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#define START_EXCEPTION(label) \
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.align 5; \
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label:
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#define FINISH_EXCEPTION(func) \
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bl transfer_to_handler_full; \
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.long func; \
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.long ret_from_except_full
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#define EXCEPTION(n, label, hdlr, xfer) \
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START_EXCEPTION(label); \
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NORMAL_EXCEPTION_PROLOG; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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xfer(n, hdlr)
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#define CRITICAL_EXCEPTION(n, label, hdlr) \
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START_EXCEPTION(label); \
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CRITICAL_EXCEPTION_PROLOG; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
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NOCOPY, crit_transfer_to_handler, \
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ret_from_crit_exc)
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#define MCHECK_EXCEPTION(n, label, hdlr) \
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START_EXCEPTION(label); \
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MCHECK_EXCEPTION_PROLOG; \
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mfspr r5,SPRN_ESR; \
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stw r5,_ESR(r11); \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
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NOCOPY, mcheck_transfer_to_handler, \
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ret_from_mcheck_exc)
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#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
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li r10,trap; \
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stw r10,TRAP(r11); \
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lis r10,msr@h; \
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ori r10,r10,msr@l; \
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copyee(r10, r9); \
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bl tfer; \
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.long hdlr; \
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.long ret
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#define COPY_EE(d, s) rlwimi d,s,0,16,16
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#define NOCOPY(d, s)
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#define EXC_XFER_STD(n, hdlr) \
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EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
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ret_from_except_full)
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#define EXC_XFER_LITE(n, hdlr) \
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EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
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ret_from_except)
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#define EXC_XFER_EE(n, hdlr) \
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EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
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ret_from_except_full)
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#define EXC_XFER_EE_LITE(n, hdlr) \
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EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
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ret_from_except)
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/* Check for a single step debug exception while in an exception
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* handler before state has been saved. This is to catch the case
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* where an instruction that we are trying to single step causes
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* an exception (eg ITLB/DTLB miss) and thus the first instruction of
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* the exception handler generates a single step debug exception.
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*
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* If we get a debug trap on the first instruction of an exception handler,
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* we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
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* a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
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* The exception handler was handling a non-critical interrupt, so it will
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* save (and later restore) the MSR via SPRN_CSRR1, which will still have
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* the MSR_DE bit set.
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*/
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#ifdef CONFIG_E200
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#define DEBUG_EXCEPTION \
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START_EXCEPTION(Debug); \
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DEBUG_EXCEPTION_PROLOG; \
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\
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/* \
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* If there is a single step or branch-taken exception in an \
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* exception entry sequence, it was probably meant to apply to \
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* the code where the exception occurred (since exception entry \
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* doesn't turn off DE automatically). We simulate the effect \
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* of turning off DE on entry to an exception handler by turning \
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* off DE in the CSRR1 value and clearing the debug status. \
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*/ \
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mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
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andis. r10,r10,DBSR_IC@h; \
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beq+ 2f; \
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\
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lis r10,KERNELBASE@h; /* check if exception in vectors */ \
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ori r10,r10,KERNELBASE@l; \
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cmplw r12,r10; \
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blt+ 2f; /* addr below exception vectors */ \
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\
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lis r10,Debug@h; \
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ori r10,r10,Debug@l; \
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cmplw r12,r10; \
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bgt+ 2f; /* addr above exception vectors */ \
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\
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/* here it looks like we got an inappropriate debug exception. */ \
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1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
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lis r10,DBSR_IC@h; /* clear the IC event */ \
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mtspr SPRN_DBSR,r10; \
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/* restore state and get out */ \
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lwz r10,_CCR(r11); \
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lwz r0,GPR0(r11); \
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lwz r1,GPR1(r11); \
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mtcrf 0x80,r10; \
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mtspr SPRN_DSRR0,r12; \
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mtspr SPRN_DSRR1,r9; \
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lwz r9,GPR9(r11); \
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lwz r12,GPR12(r11); \
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mtspr DEBUG_SPRG,r8; \
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BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
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lwz r10,GPR10-INT_FRAME_SIZE(r8); \
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lwz r11,GPR11-INT_FRAME_SIZE(r8); \
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mfspr r8,DEBUG_SPRG; \
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\
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RFDI; \
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b .; \
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\
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/* continue normal handling for a critical exception... */ \
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2: mfspr r4,SPRN_DBSR; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
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#else
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#define DEBUG_EXCEPTION \
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START_EXCEPTION(Debug); \
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CRITICAL_EXCEPTION_PROLOG; \
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\
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/* \
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* If there is a single step or branch-taken exception in an \
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* exception entry sequence, it was probably meant to apply to \
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* the code where the exception occurred (since exception entry \
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* doesn't turn off DE automatically). We simulate the effect \
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* of turning off DE on entry to an exception handler by turning \
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* off DE in the CSRR1 value and clearing the debug status. \
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*/ \
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mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
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andis. r10,r10,DBSR_IC@h; \
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beq+ 2f; \
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\
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lis r10,KERNELBASE@h; /* check if exception in vectors */ \
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ori r10,r10,KERNELBASE@l; \
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cmplw r12,r10; \
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blt+ 2f; /* addr below exception vectors */ \
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\
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lis r10,Debug@h; \
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ori r10,r10,Debug@l; \
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cmplw r12,r10; \
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bgt+ 2f; /* addr above exception vectors */ \
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\
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/* here it looks like we got an inappropriate debug exception. */ \
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1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
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lis r10,DBSR_IC@h; /* clear the IC event */ \
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mtspr SPRN_DBSR,r10; \
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/* restore state and get out */ \
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lwz r10,_CCR(r11); \
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lwz r0,GPR0(r11); \
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lwz r1,GPR1(r11); \
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mtcrf 0x80,r10; \
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mtspr SPRN_CSRR0,r12; \
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mtspr SPRN_CSRR1,r9; \
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lwz r9,GPR9(r11); \
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lwz r12,GPR12(r11); \
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mtspr CRIT_SPRG,r8; \
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BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
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lwz r10,GPR10-INT_FRAME_SIZE(r8); \
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lwz r11,GPR11-INT_FRAME_SIZE(r8); \
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mfspr r8,CRIT_SPRG; \
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\
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rfci; \
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b .; \
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\
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/* continue normal handling for a critical exception... */ \
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2: mfspr r4,SPRN_DBSR; \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
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#endif
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#define INSTRUCTION_STORAGE_EXCEPTION \
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START_EXCEPTION(InstructionStorage) \
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NORMAL_EXCEPTION_PROLOG; \
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mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
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stw r5,_ESR(r11); \
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mr r4,r12; /* Pass SRR0 as arg2 */ \
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li r5,0; /* Pass zero as arg3 */ \
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EXC_XFER_EE_LITE(0x0400, handle_page_fault)
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#define ALIGNMENT_EXCEPTION \
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START_EXCEPTION(Alignment) \
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NORMAL_EXCEPTION_PROLOG; \
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mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
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stw r4,_DEAR(r11); \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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EXC_XFER_EE(0x0600, alignment_exception)
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#define PROGRAM_EXCEPTION \
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START_EXCEPTION(Program) \
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NORMAL_EXCEPTION_PROLOG; \
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mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
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stw r4,_ESR(r11); \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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EXC_XFER_STD(0x0700, program_check_exception)
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#define DECREMENTER_EXCEPTION \
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START_EXCEPTION(Decrementer) \
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NORMAL_EXCEPTION_PROLOG; \
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lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
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mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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EXC_XFER_LITE(0x0900, timer_interrupt)
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#define FP_UNAVAILABLE_EXCEPTION \
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START_EXCEPTION(FloatingPointUnavailable) \
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NORMAL_EXCEPTION_PROLOG; \
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bne load_up_fpu; /* if from user, just load it up */ \
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addi r3,r1,STACK_FRAME_OVERHEAD; \
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EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
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#endif /* __HEAD_BOOKE_H__ */
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