74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/*
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* Copyright 2007-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_BLACKFIN_H_
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#define _MACH_BLACKFIN_H_
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#include "bf548.h"
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#include "anomaly.h"
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#ifdef CONFIG_BF542
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#include "defBF542.h"
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#endif
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#ifdef CONFIG_BF544
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#include "defBF544.h"
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#endif
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#ifdef CONFIG_BF547
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#include "defBF547.h"
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#endif
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#ifdef CONFIG_BF548
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#include "defBF548.h"
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#endif
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#ifdef CONFIG_BF549
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#include "defBF549.h"
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#endif
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#if !defined(__ASSEMBLY__)
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#ifdef CONFIG_BF542
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#include "cdefBF542.h"
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#endif
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#ifdef CONFIG_BF544
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#include "cdefBF544.h"
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#endif
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#ifdef CONFIG_BF547
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#include "cdefBF547.h"
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#endif
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#ifdef CONFIG_BF548
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#include "cdefBF548.h"
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#endif
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#ifdef CONFIG_BF549
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#include "cdefBF549.h"
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#endif
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#endif
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#define BFIN_UART_NR_PORTS 4
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#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
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#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
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#define OFFSET_GCTL 0x08 /* Global Control Register */
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#define OFFSET_LCR 0x0C /* Line Control Register */
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#define OFFSET_MCR 0x10 /* Modem Control Register */
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#define OFFSET_LSR 0x14 /* Line Status Register */
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#define OFFSET_MSR 0x18 /* Modem Status Register */
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#define OFFSET_SCR 0x1C /* SCR Scratch Register */
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#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
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#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
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#define OFFSET_THR 0x28 /* Transmit Holding register */
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#define OFFSET_RBR 0x2C /* Receive Buffer register */
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/* PLL_DIV Masks */
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#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
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#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
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#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
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#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
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#endif
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