754 lines
18 KiB
C
754 lines
18 KiB
C
/*
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* Clock implementation for VIA/Wondermedia SoC's
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#define LEGACY_PMC_BASE 0xD8130000
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/* All clocks share the same lock as none can be changed concurrently */
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static DEFINE_SPINLOCK(_lock);
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struct clk_device {
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struct clk_hw hw;
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void __iomem *div_reg;
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unsigned int div_mask;
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void __iomem *en_reg;
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int en_bit;
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spinlock_t *lock;
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};
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/*
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* Add new PLL_TYPE_x definitions here as required. Use the first known model
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* to support the new type as the name.
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* Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
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* vtwm_pll_set_rate() to handle the new PLL_TYPE_x
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*/
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#define PLL_TYPE_VT8500 0
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#define PLL_TYPE_WM8650 1
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#define PLL_TYPE_WM8750 2
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#define PLL_TYPE_WM8850 3
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struct clk_pll {
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struct clk_hw hw;
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void __iomem *reg;
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spinlock_t *lock;
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int type;
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};
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static void __iomem *pmc_base;
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static __init void vtwm_set_pmc_base(void)
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{
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struct device_node *np =
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of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
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if (np)
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pmc_base = of_iomap(np, 0);
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else
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pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
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of_node_put(np);
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if (!pmc_base)
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pr_err("%s:of_iomap(pmc) failed\n", __func__);
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}
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#define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
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#define VT8500_PMC_BUSY_MASK 0x18
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static void vt8500_pmc_wait_busy(void)
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{
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while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
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cpu_relax();
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}
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static int vt8500_dclk_enable(struct clk_hw *hw)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 en_val;
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unsigned long flags = 0;
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spin_lock_irqsave(cdev->lock, flags);
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en_val = readl(cdev->en_reg);
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en_val |= BIT(cdev->en_bit);
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writel(en_val, cdev->en_reg);
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spin_unlock_irqrestore(cdev->lock, flags);
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return 0;
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}
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static void vt8500_dclk_disable(struct clk_hw *hw)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 en_val;
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unsigned long flags = 0;
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spin_lock_irqsave(cdev->lock, flags);
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en_val = readl(cdev->en_reg);
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en_val &= ~BIT(cdev->en_bit);
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writel(en_val, cdev->en_reg);
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spin_unlock_irqrestore(cdev->lock, flags);
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}
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static int vt8500_dclk_is_enabled(struct clk_hw *hw)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
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return en_val ? 1 : 0;
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}
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static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 div = readl(cdev->div_reg) & cdev->div_mask;
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/* Special case for SDMMC devices */
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if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
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div = 64 * (div & 0x1f);
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/* div == 0 is actually the highest divisor */
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if (div == 0)
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div = (cdev->div_mask + 1);
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return parent_rate / div;
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}
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static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 divisor;
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if (rate == 0)
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return 0;
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divisor = *prate / rate;
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/* If prate / rate would be decimal, incr the divisor */
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if (rate * divisor < *prate)
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divisor++;
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/*
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* If this is a request for SDMMC we have to adjust the divisor
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* when >31 to use the fixed predivisor
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*/
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if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
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divisor = 64 * ((divisor / 64) + 1);
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}
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return *prate / divisor;
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}
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static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 divisor;
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unsigned long flags = 0;
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if (rate == 0)
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return 0;
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divisor = parent_rate / rate;
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if (divisor == cdev->div_mask + 1)
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divisor = 0;
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/* SDMMC mask may need to be corrected before testing if its valid */
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if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
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/*
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* Bit 5 is a fixed /64 predivisor. If the requested divisor
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* is >31 then correct for the fixed divisor being required.
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*/
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divisor = 0x20 + (divisor / 64);
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}
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if (divisor > cdev->div_mask) {
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pr_err("%s: invalid divisor for clock\n", __func__);
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return -EINVAL;
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}
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spin_lock_irqsave(cdev->lock, flags);
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vt8500_pmc_wait_busy();
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writel(divisor, cdev->div_reg);
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vt8500_pmc_wait_busy();
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spin_unlock_irqrestore(cdev->lock, flags);
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return 0;
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}
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static const struct clk_ops vt8500_gated_clk_ops = {
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.enable = vt8500_dclk_enable,
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.disable = vt8500_dclk_disable,
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.is_enabled = vt8500_dclk_is_enabled,
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};
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static const struct clk_ops vt8500_divisor_clk_ops = {
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.round_rate = vt8500_dclk_round_rate,
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.set_rate = vt8500_dclk_set_rate,
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.recalc_rate = vt8500_dclk_recalc_rate,
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};
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static const struct clk_ops vt8500_gated_divisor_clk_ops = {
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.enable = vt8500_dclk_enable,
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.disable = vt8500_dclk_disable,
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.is_enabled = vt8500_dclk_is_enabled,
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.round_rate = vt8500_dclk_round_rate,
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.set_rate = vt8500_dclk_set_rate,
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.recalc_rate = vt8500_dclk_recalc_rate,
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};
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#define CLK_INIT_GATED BIT(0)
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#define CLK_INIT_DIVISOR BIT(1)
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#define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
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static __init void vtwm_device_clk_init(struct device_node *node)
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{
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u32 en_reg, div_reg;
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struct clk_hw *hw;
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struct clk_device *dev_clk;
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const char *clk_name = node->name;
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const char *parent_name;
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struct clk_init_data init;
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int rc;
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int clk_init_flags = 0;
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if (!pmc_base)
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vtwm_set_pmc_base();
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dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
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if (WARN_ON(!dev_clk))
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return;
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dev_clk->lock = &_lock;
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rc = of_property_read_u32(node, "enable-reg", &en_reg);
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if (!rc) {
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dev_clk->en_reg = pmc_base + en_reg;
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rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
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if (rc) {
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pr_err("%s: enable-bit property required for gated clock\n",
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__func__);
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return;
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}
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clk_init_flags |= CLK_INIT_GATED;
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}
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rc = of_property_read_u32(node, "divisor-reg", &div_reg);
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if (!rc) {
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dev_clk->div_reg = pmc_base + div_reg;
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/*
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* use 0x1f as the default mask since it covers
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* almost all the clocks and reduces dts properties
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*/
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dev_clk->div_mask = 0x1f;
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of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
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clk_init_flags |= CLK_INIT_DIVISOR;
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}
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of_property_read_string(node, "clock-output-names", &clk_name);
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switch (clk_init_flags) {
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case CLK_INIT_GATED:
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init.ops = &vt8500_gated_clk_ops;
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break;
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case CLK_INIT_DIVISOR:
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init.ops = &vt8500_divisor_clk_ops;
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break;
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case CLK_INIT_GATED_DIVISOR:
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init.ops = &vt8500_gated_divisor_clk_ops;
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break;
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default:
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pr_err("%s: Invalid clock description in device tree\n",
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__func__);
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kfree(dev_clk);
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return;
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}
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init.name = clk_name;
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init.flags = 0;
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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dev_clk->hw.init = &init;
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hw = &dev_clk->hw;
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rc = clk_hw_register(NULL, hw);
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if (WARN_ON(rc)) {
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kfree(dev_clk);
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return;
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}
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rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
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clk_hw_register_clkdev(hw, clk_name, NULL);
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}
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CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
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/* PLL clock related functions */
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#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
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/* Helper macros for PLL_VT8500 */
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#define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
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#define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
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#define VT8500_BITS_TO_FREQ(r, m, d) \
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((r / d) * m)
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#define VT8500_BITS_TO_VAL(m, d) \
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((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
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/* Helper macros for PLL_WM8650 */
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#define WM8650_PLL_MUL(x) (x & 0x3FF)
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#define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
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#define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
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(r * m / (d1 * (1 << d2)))
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#define WM8650_BITS_TO_VAL(m, d1, d2) \
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((d2 << 13) | (d1 << 10) | (m & 0x3FF))
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/* Helper macros for PLL_WM8750 */
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#define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1)
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#define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
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#define WM8750_BITS_TO_FREQ(r, m, d1, d2) \
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(r * (m+1) / ((d1+1) * (1 << d2)))
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#define WM8750_BITS_TO_VAL(f, m, d1, d2) \
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((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
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/* Helper macros for PLL_WM8850 */
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#define WM8850_PLL_MUL(x) ((((x >> 16) & 0x7F) + 1) * 2)
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#define WM8850_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 3)))
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#define WM8850_BITS_TO_FREQ(r, m, d1, d2) \
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(r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
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#define WM8850_BITS_TO_VAL(m, d1, d2) \
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((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
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static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
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u32 *multiplier, u32 *prediv)
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{
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unsigned long tclk;
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/* sanity check */
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if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
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pr_err("%s: requested rate out of range\n", __func__);
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*multiplier = 0;
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*prediv = 1;
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return -EINVAL;
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}
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if (rate <= parent_rate * 31)
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/* use the prediv to double the resolution */
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*prediv = 2;
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else
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*prediv = 1;
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*multiplier = rate / (parent_rate / *prediv);
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tclk = (parent_rate / *prediv) * *multiplier;
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if (tclk != rate)
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pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
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rate, tclk);
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return 0;
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}
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/*
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* M * parent [O1] => / P [O2] => / D [O3]
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* Where O1 is 900MHz...3GHz;
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* O2 is 600MHz >= (M * parent) / P >= 300MHz;
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* M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
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* Possible ranges (O3):
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* D = 8: 37,5MHz...75MHz
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* D = 4: 75MHz...150MHz
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* D = 2: 150MHz...300MHz
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* D = 1: 300MHz...600MHz
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*/
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static int wm8650_find_pll_bits(unsigned long rate,
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unsigned long parent_rate, u32 *multiplier, u32 *divisor1,
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u32 *divisor2)
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{
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unsigned long O1, min_err, rate_err;
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if (!parent_rate || (rate < 37500000) || (rate > 600000000))
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return -EINVAL;
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*divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 :
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rate <= 300000000 ? 1 : 0;
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/*
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* Divisor P cannot be calculated. Test all divisors and find where M
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* will be as close as possible to the requested rate.
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*/
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min_err = ULONG_MAX;
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for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) {
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O1 = rate * *divisor1 * (1 << (*divisor2));
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rate_err = O1 % parent_rate;
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if (rate_err < min_err) {
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*multiplier = O1 / parent_rate;
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if (rate_err == 0)
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return 0;
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min_err = rate_err;
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}
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}
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if ((*multiplier < 3) || (*multiplier > 1023))
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return -EINVAL;
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pr_warn("%s: rate error is %lu\n", __func__, min_err);
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return 0;
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}
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static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
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{
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/* calculate frequency (MHz) after pre-divisor */
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u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
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if ((freq < 10) || (freq > 200))
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pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
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__func__, freq);
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if (freq >= 166)
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return 7;
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else if (freq >= 104)
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return 6;
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else if (freq >= 65)
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return 5;
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else if (freq >= 42)
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return 4;
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else if (freq >= 26)
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return 3;
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else if (freq >= 16)
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return 2;
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else if (freq >= 10)
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return 1;
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return 0;
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}
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static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
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u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
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{
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u32 mul;
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int div1, div2;
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unsigned long tclk, rate_err, best_err;
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best_err = (unsigned long)-1;
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/* Find the closest match (lower or equal to requested) */
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for (div1 = 1; div1 >= 0; div1--)
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for (div2 = 7; div2 >= 0; div2--)
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for (mul = 0; mul <= 255; mul++) {
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tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
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if (tclk > rate)
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continue;
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/* error will always be +ve */
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rate_err = rate - tclk;
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if (rate_err == 0) {
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*filter = wm8750_get_filter(parent_rate, div1);
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*multiplier = mul;
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*divisor1 = div1;
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*divisor2 = div2;
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return 0;
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}
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if (rate_err < best_err) {
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best_err = rate_err;
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*multiplier = mul;
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*divisor1 = div1;
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*divisor2 = div2;
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}
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}
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if (best_err == (unsigned long)-1) {
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pr_warn("%s: impossible rate %lu\n", __func__, rate);
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return -EINVAL;
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}
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/* if we got here, it wasn't an exact match */
|
|
pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
|
|
rate - best_err);
|
|
|
|
*filter = wm8750_get_filter(parent_rate, *divisor1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
|
|
u32 *multiplier, u32 *divisor1, u32 *divisor2)
|
|
{
|
|
u32 mul;
|
|
int div1, div2;
|
|
unsigned long tclk, rate_err, best_err;
|
|
|
|
best_err = (unsigned long)-1;
|
|
|
|
/* Find the closest match (lower or equal to requested) */
|
|
for (div1 = 1; div1 >= 0; div1--)
|
|
for (div2 = 3; div2 >= 0; div2--)
|
|
for (mul = 0; mul <= 127; mul++) {
|
|
tclk = parent_rate * ((mul + 1) * 2) /
|
|
((div1 + 1) * (1 << div2));
|
|
if (tclk > rate)
|
|
continue;
|
|
/* error will always be +ve */
|
|
rate_err = rate - tclk;
|
|
if (rate_err == 0) {
|
|
*multiplier = mul;
|
|
*divisor1 = div1;
|
|
*divisor2 = div2;
|
|
return 0;
|
|
}
|
|
|
|
if (rate_err < best_err) {
|
|
best_err = rate_err;
|
|
*multiplier = mul;
|
|
*divisor1 = div1;
|
|
*divisor2 = div2;
|
|
}
|
|
}
|
|
|
|
if (best_err == (unsigned long)-1) {
|
|
pr_warn("%s: impossible rate %lu\n", __func__, rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* if we got here, it wasn't an exact match */
|
|
pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
|
|
rate - best_err);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_pll *pll = to_clk_pll(hw);
|
|
u32 filter, mul, div1, div2;
|
|
u32 pll_val;
|
|
unsigned long flags = 0;
|
|
int ret;
|
|
|
|
/* sanity check */
|
|
|
|
switch (pll->type) {
|
|
case PLL_TYPE_VT8500:
|
|
ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
|
|
if (!ret)
|
|
pll_val = VT8500_BITS_TO_VAL(mul, div1);
|
|
break;
|
|
case PLL_TYPE_WM8650:
|
|
ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
|
|
if (!ret)
|
|
pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
|
|
break;
|
|
case PLL_TYPE_WM8750:
|
|
ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
|
|
if (!ret)
|
|
pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
|
|
break;
|
|
case PLL_TYPE_WM8850:
|
|
ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
|
|
if (!ret)
|
|
pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
|
|
break;
|
|
default:
|
|
pr_err("%s: invalid pll type\n", __func__);
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
spin_lock_irqsave(pll->lock, flags);
|
|
|
|
vt8500_pmc_wait_busy();
|
|
writel(pll_val, pll->reg);
|
|
vt8500_pmc_wait_busy();
|
|
|
|
spin_unlock_irqrestore(pll->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *prate)
|
|
{
|
|
struct clk_pll *pll = to_clk_pll(hw);
|
|
u32 filter, mul, div1, div2;
|
|
long round_rate;
|
|
int ret;
|
|
|
|
switch (pll->type) {
|
|
case PLL_TYPE_VT8500:
|
|
ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1);
|
|
if (!ret)
|
|
round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
|
|
break;
|
|
case PLL_TYPE_WM8650:
|
|
ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
|
|
if (!ret)
|
|
round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
|
|
break;
|
|
case PLL_TYPE_WM8750:
|
|
ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
|
|
if (!ret)
|
|
round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
|
|
break;
|
|
case PLL_TYPE_WM8850:
|
|
ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
|
|
if (!ret)
|
|
round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
return round_rate;
|
|
}
|
|
|
|
static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_pll *pll = to_clk_pll(hw);
|
|
u32 pll_val = readl(pll->reg);
|
|
unsigned long pll_freq;
|
|
|
|
switch (pll->type) {
|
|
case PLL_TYPE_VT8500:
|
|
pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
|
|
pll_freq /= VT8500_PLL_DIV(pll_val);
|
|
break;
|
|
case PLL_TYPE_WM8650:
|
|
pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
|
|
pll_freq /= WM8650_PLL_DIV(pll_val);
|
|
break;
|
|
case PLL_TYPE_WM8750:
|
|
pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
|
|
pll_freq /= WM8750_PLL_DIV(pll_val);
|
|
break;
|
|
case PLL_TYPE_WM8850:
|
|
pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
|
|
pll_freq /= WM8850_PLL_DIV(pll_val);
|
|
break;
|
|
default:
|
|
pll_freq = 0;
|
|
}
|
|
|
|
return pll_freq;
|
|
}
|
|
|
|
static const struct clk_ops vtwm_pll_ops = {
|
|
.round_rate = vtwm_pll_round_rate,
|
|
.set_rate = vtwm_pll_set_rate,
|
|
.recalc_rate = vtwm_pll_recalc_rate,
|
|
};
|
|
|
|
static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
|
|
{
|
|
u32 reg;
|
|
struct clk_hw *hw;
|
|
struct clk_pll *pll_clk;
|
|
const char *clk_name = node->name;
|
|
const char *parent_name;
|
|
struct clk_init_data init;
|
|
int rc;
|
|
|
|
if (!pmc_base)
|
|
vtwm_set_pmc_base();
|
|
|
|
rc = of_property_read_u32(node, "reg", ®);
|
|
if (WARN_ON(rc))
|
|
return;
|
|
|
|
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
|
|
if (WARN_ON(!pll_clk))
|
|
return;
|
|
|
|
pll_clk->reg = pmc_base + reg;
|
|
pll_clk->lock = &_lock;
|
|
pll_clk->type = pll_type;
|
|
|
|
of_property_read_string(node, "clock-output-names", &clk_name);
|
|
|
|
init.name = clk_name;
|
|
init.ops = &vtwm_pll_ops;
|
|
init.flags = 0;
|
|
parent_name = of_clk_get_parent_name(node, 0);
|
|
init.parent_names = &parent_name;
|
|
init.num_parents = 1;
|
|
|
|
pll_clk->hw.init = &init;
|
|
|
|
hw = &pll_clk->hw;
|
|
rc = clk_hw_register(NULL, &pll_clk->hw);
|
|
if (WARN_ON(rc)) {
|
|
kfree(pll_clk);
|
|
return;
|
|
}
|
|
rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
|
|
clk_hw_register_clkdev(hw, clk_name, NULL);
|
|
}
|
|
|
|
|
|
/* Wrappers for initialization functions */
|
|
|
|
static void __init vt8500_pll_init(struct device_node *node)
|
|
{
|
|
vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
|
|
}
|
|
CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
|
|
|
|
static void __init wm8650_pll_init(struct device_node *node)
|
|
{
|
|
vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
|
|
}
|
|
CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
|
|
|
|
static void __init wm8750_pll_init(struct device_node *node)
|
|
{
|
|
vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
|
|
}
|
|
CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
|
|
|
|
static void __init wm8850_pll_init(struct device_node *node)
|
|
{
|
|
vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
|
|
}
|
|
CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);
|