262 lines
7.0 KiB
C
262 lines
7.0 KiB
C
/* sun4c_irq.c
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* arch/sparc/kernel/sun4c_irq.c:
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*
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* djhr: Hacked out of irq.c into a CPU dependent version.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
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* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
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*/
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include "irq.h"
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/psr.h>
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#include <asm/vaddrs.h>
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#include <asm/timer.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/traps.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/sun4paddr.h>
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#include <asm/idprom.h>
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#include <asm/machines.h>
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#include <asm/sbus.h>
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#if 0
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static struct resource sun4c_timer_eb = { "sun4c_timer" };
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static struct resource sun4c_intr_eb = { "sun4c_intr" };
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#endif
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/*
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* Bit field defines for the interrupt registers on various
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* Sparc machines.
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*/
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/* The sun4c interrupt register. */
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#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
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#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
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#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
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#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
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#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
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#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
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#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
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/* Pointer to the interrupt enable byte
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*
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* Dave Redman (djhr@tadpole.co.uk)
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* What you may not be aware of is that entry.S requires this variable.
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*
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* --- linux_trap_nmi_sun4c --
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*
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* so don't go making it static, like I tried. sigh.
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*/
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unsigned char *interrupt_enable = NULL;
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static int sun4c_pil_map[] = { 0, 1, 2, 3, 5, 7, 8, 9 };
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unsigned int sun4c_sbint_to_irq(struct sbus_dev *sdev, unsigned int sbint)
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{
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if (sbint >= sizeof(sun4c_pil_map)) {
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printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
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BUG();
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}
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return sun4c_pil_map[sbint];
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}
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static void sun4c_disable_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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unsigned char current_mask, new_mask;
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local_irq_save(flags);
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irq_nr &= (NR_IRQS - 1);
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current_mask = *interrupt_enable;
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switch(irq_nr) {
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case 1:
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new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
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break;
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case 8:
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new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
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break;
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case 10:
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new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
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break;
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case 14:
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new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
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break;
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default:
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local_irq_restore(flags);
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return;
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}
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*interrupt_enable = new_mask;
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local_irq_restore(flags);
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}
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static void sun4c_enable_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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unsigned char current_mask, new_mask;
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local_irq_save(flags);
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irq_nr &= (NR_IRQS - 1);
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current_mask = *interrupt_enable;
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switch(irq_nr) {
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case 1:
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new_mask = ((current_mask) | SUN4C_INT_E1);
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break;
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case 8:
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new_mask = ((current_mask) | SUN4C_INT_E8);
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break;
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case 10:
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new_mask = ((current_mask) | SUN4C_INT_E10);
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break;
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case 14:
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new_mask = ((current_mask) | SUN4C_INT_E14);
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break;
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default:
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local_irq_restore(flags);
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return;
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}
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*interrupt_enable = new_mask;
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local_irq_restore(flags);
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}
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#define TIMER_IRQ 10 /* Also at level 14, but we ignore that one. */
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#define PROFILE_IRQ 14 /* Level14 ticker.. used by OBP for polling */
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volatile struct sun4c_timer_info *sun4c_timers;
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#ifdef CONFIG_SUN4
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/* This is an ugly hack to work around the
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current timer code, and make it work with
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the sun4/260 intersil
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*/
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volatile struct sun4c_timer_info sun4_timer;
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#endif
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static void sun4c_clear_clock_irq(void)
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{
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volatile unsigned int clear_intr;
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#ifdef CONFIG_SUN4
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if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
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clear_intr = sun4_timer.timer_limit10;
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else
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#endif
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clear_intr = sun4c_timers->timer_limit10;
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}
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static void sun4c_clear_profile_irq(int cpu)
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{
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/* Errm.. not sure how to do this.. */
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}
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static void sun4c_load_profile_irq(int cpu, unsigned int limit)
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{
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/* Errm.. not sure how to do this.. */
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}
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static void __init sun4c_init_timers(irq_handler_t counter_fn)
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{
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int irq;
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/* Map the Timer chip, this is implemented in hardware inside
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* the cache chip on the sun4c.
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*/
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#ifdef CONFIG_SUN4
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if (idprom->id_machtype == (SM_SUN4 | SM_4_260))
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sun4c_timers = &sun4_timer;
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else
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#endif
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sun4c_timers = ioremap(SUN_TIMER_PHYSADDR,
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sizeof(struct sun4c_timer_info));
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/* Have the level 10 timer tick at 100HZ. We don't touch the
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* level 14 timer limit since we are letting the prom handle
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* them until we have a real console driver so L1-A works.
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*/
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sun4c_timers->timer_limit10 = (((1000000/HZ) + 1) << 10);
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master_l10_counter = &sun4c_timers->cur_count10;
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master_l10_limit = &sun4c_timers->timer_limit10;
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irq = request_irq(TIMER_IRQ,
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counter_fn,
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(IRQF_DISABLED | SA_STATIC_ALLOC),
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"timer", NULL);
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if (irq) {
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prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
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prom_halt();
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}
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#if 0
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/* This does not work on 4/330 */
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sun4c_enable_irq(10);
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#endif
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claim_ticker14(NULL, PROFILE_IRQ, 0);
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}
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#ifdef CONFIG_SMP
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static void sun4c_nop(void) {}
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#endif
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void __init sun4c_init_IRQ(void)
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{
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struct linux_prom_registers int_regs[2];
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int ie_node;
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if (ARCH_SUN4) {
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interrupt_enable = (char *)
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ioremap(sun4_ie_physaddr, PAGE_SIZE);
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} else {
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struct resource phyres;
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ie_node = prom_searchsiblings (prom_getchild(prom_root_node),
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"interrupt-enable");
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if(ie_node == 0)
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panic("Cannot find /interrupt-enable node");
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/* Depending on the "address" property is bad news... */
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interrupt_enable = NULL;
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if (prom_getproperty(ie_node, "reg", (char *) int_regs,
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sizeof(int_regs)) != -1) {
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memset(&phyres, 0, sizeof(struct resource));
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phyres.flags = int_regs[0].which_io;
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phyres.start = int_regs[0].phys_addr;
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interrupt_enable = (char *) sbus_ioremap(&phyres, 0,
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int_regs[0].reg_size, "sun4c_intr");
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}
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}
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if (!interrupt_enable)
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panic("Cannot map interrupt_enable");
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BTFIXUPSET_CALL(sbint_to_irq, sun4c_sbint_to_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(clear_profile_irq, sun4c_clear_profile_irq, BTFIXUPCALL_NOP);
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BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
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sparc_init_timers = sun4c_init_timers;
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#ifdef CONFIG_SMP
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BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
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BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
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BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
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#endif
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*interrupt_enable = (SUN4C_INT_ENABLE);
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/* Cannot enable interrupts until OBP ticker is disabled. */
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}
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