210 lines
3.0 KiB
ArmAsm
210 lines
3.0 KiB
ArmAsm
/*
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* arch/xtensa/mm/misc.S
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*
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* Miscellaneous assembly functions.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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*/
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/* Note: we might want to implement some of the loops as zero-overhead-loops,
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* where applicable and if supported by the processor.
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*/
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#include <linux/linkage.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheasm.h>
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/* clear_page (page) */
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ENTRY(clear_page)
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entry a1, 16
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addi a4, a2, PAGE_SIZE
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movi a3, 0
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1: s32i a3, a2, 0
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s32i a3, a2, 4
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s32i a3, a2, 8
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s32i a3, a2, 12
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s32i a3, a2, 16
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s32i a3, a2, 20
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s32i a3, a2, 24
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s32i a3, a2, 28
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addi a2, a2, 32
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blt a2, a4, 1b
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retw
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/*
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* copy_page (void *to, void *from)
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* a2 a3
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*/
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ENTRY(copy_page)
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entry a1, 16
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addi a4, a2, PAGE_SIZE
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1: l32i a5, a3, 0
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l32i a6, a3, 4
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l32i a7, a3, 8
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s32i a5, a2, 0
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s32i a6, a2, 4
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s32i a7, a2, 8
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l32i a5, a3, 12
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l32i a6, a3, 16
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l32i a7, a3, 20
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s32i a5, a2, 12
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s32i a6, a2, 16
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s32i a7, a2, 20
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l32i a5, a3, 24
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l32i a6, a3, 28
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s32i a5, a2, 24
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s32i a6, a2, 28
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addi a2, a2, 32
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addi a3, a3, 32
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blt a2, a4, 1b
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retw
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/*
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* void __invalidate_icache_page(ulong start)
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*/
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ENTRY(__invalidate_icache_page)
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entry sp, 16
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___invalidate_icache_page a2 a3
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isync
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retw
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/*
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* void __invalidate_dcache_page(ulong start)
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*/
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ENTRY(__invalidate_dcache_page)
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entry sp, 16
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___invalidate_dcache_page a2 a3
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dsync
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retw
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/*
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* void __flush_invalidate_dcache_page(ulong start)
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*/
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ENTRY(__flush_invalidate_dcache_page)
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entry sp, 16
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___flush_invalidate_dcache_page a2 a3
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dsync
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retw
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/*
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* void __flush_dcache_page(ulong start)
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*/
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ENTRY(__flush_dcache_page)
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entry sp, 16
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___flush_dcache_page a2 a3
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dsync
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retw
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/*
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* void __invalidate_icache_range(ulong start, ulong size)
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*/
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ENTRY(__invalidate_icache_range)
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entry sp, 16
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___invalidate_icache_range a2 a3 a4
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isync
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retw
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/*
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* void __flush_invalidate_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__flush_invalidate_dcache_range)
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entry sp, 16
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___flush_invalidate_dcache_range a2 a3 a4
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dsync
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retw
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/*
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* void _flush_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__flush_dcache_range)
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entry sp, 16
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___flush_dcache_range a2 a3 a4
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dsync
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retw
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/*
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* void _invalidate_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__invalidate_dcache_range)
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entry sp, 16
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___invalidate_dcache_range a2 a3 a4
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retw
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/*
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* void _invalidate_icache_all(void)
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*/
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ENTRY(__invalidate_icache_all)
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entry sp, 16
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___invalidate_icache_all a2 a3
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isync
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retw
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/*
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* void _flush_invalidate_dcache_all(void)
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*/
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ENTRY(__flush_invalidate_dcache_all)
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entry sp, 16
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___flush_invalidate_dcache_all a2 a3
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dsync
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retw
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/*
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* void _invalidate_dcache_all(void)
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*/
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ENTRY(__invalidate_dcache_all)
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entry sp, 16
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___invalidate_dcache_all a2 a3
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dsync
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retw
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