Chris Metcalf cd6f32aa08 arch/tile: support <asm/cachectl.h> header for cacheflush() syscall ... We already had a syscall that did some dcache flushing, but it was not used in practice. Make it MIPS compatible instead so it can do both the DCACHE and ICACHE actions. We have code that wants to be able to use the ICACHE flush mode from userspace so this change enables that. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>		2012-05-25 12:48:24 -04:00
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arch	arch/tile: fix typo in <arch/spr_def.h>	2012-04-02 12:00:14 -04:00
asm	arch/tile: support <asm/cachectl.h> header for cacheflush() syscall	2012-05-25 12:48:24 -04:00
hv	arch/tile: Allow tilegx to build with either 16K or 64K page size	2012-05-25 12:48:24 -04:00