235 lines
6.3 KiB
C
235 lines
6.3 KiB
C
/*
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* arch/v850/kernel/as85ep1.c -- AS85EP1 V850E evaluation chip/board
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*
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* Copyright (C) 2002,03 NEC Electronics Corporation
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* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/major.h>
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#include <linux/irq.h>
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#include <asm/machdep.h>
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#include <asm/atomic.h>
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#include <asm/page.h>
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#include <asm/v850e_timer_d.h>
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#include <asm/v850e_uart.h>
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#include "mach.h"
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/* SRAM and SDRAM are vaguely contiguous (with a big hole in between; see
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mach_reserve_bootmem for details); use both as one big area. */
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#define RAM_START SRAM_ADDR
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#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
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/* The bits of this port are connected to an 8-LED bar-graph. */
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#define LEDS_PORT 4
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static void as85ep1_led_tick (void);
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extern char _intv_copy_src_start, _intv_copy_src_end;
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extern char _intv_copy_dst_start;
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void __init mach_early_init (void)
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{
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#ifndef CONFIG_ROM_KERNEL
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const u32 *src;
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register u32 *dst asm ("ep");
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#endif
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AS85EP1_CSC(0) = 0x0403;
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AS85EP1_BCT(0) = 0xB8B8;
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AS85EP1_DWC(0) = 0x0104;
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AS85EP1_BCC = 0x0012;
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AS85EP1_ASC = 0;
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AS85EP1_LBS = 0x00A9;
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AS85EP1_PORT_PMC(6) = 0xFF; /* valid A0,A1,A20-A25 */
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AS85EP1_PORT_PMC(7) = 0x0E; /* valid CS1-CS3 */
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AS85EP1_PORT_PMC(9) = 0xFF; /* valid D16-D23 */
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AS85EP1_PORT_PMC(10) = 0xFF; /* valid D24-D31 */
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AS85EP1_RFS(1) = 0x800c;
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AS85EP1_RFS(3) = 0x800c;
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AS85EP1_SCR(1) = 0x20A9;
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AS85EP1_SCR(3) = 0x20A9;
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#ifndef CONFIG_ROM_KERNEL
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/* The early chip we have is buggy, and writing the interrupt
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vectors into low RAM may screw up, so for non-ROM kernels, we
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only rely on the reset vector being downloaded, and copy the
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rest of the interrupt vectors into place here. The specific bug
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is that writing address N, where (N & 0x10) == 0x10, will _also_
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write to address (N - 0x10). We avoid this (effectively) by
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writing in 16-byte chunks backwards from the end. */
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AS85EP1_IRAMM = 0x3; /* "write-mode" for the internal instruction memory */
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src = (u32 *)(((u32)&_intv_copy_src_end - 1) & ~0xF);
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dst = (u32 *)&_intv_copy_dst_start
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+ (src - (u32 *)&_intv_copy_src_start);
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do {
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u32 t0 = src[0], t1 = src[1], t2 = src[2], t3 = src[3];
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dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;
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dst -= 4;
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src -= 4;
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} while (src > (u32 *)&_intv_copy_src_start);
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AS85EP1_IRAMM = 0x0; /* "read-mode" for the internal instruction memory */
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#endif /* !CONFIG_ROM_KERNEL */
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v850e_intc_disable_irqs ();
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}
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void __init mach_setup (char **cmdline)
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{
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AS85EP1_PORT_PMC (LEDS_PORT) = 0; /* Make the LEDs port an I/O port. */
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AS85EP1_PORT_PM (LEDS_PORT) = 0; /* Make all the bits output pins. */
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mach_tick = as85ep1_led_tick;
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}
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void __init mach_get_physical_ram (unsigned long *ram_start,
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unsigned long *ram_len)
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{
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*ram_start = RAM_START;
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*ram_len = RAM_END - RAM_START;
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}
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/* Convenience macros. */
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#define SRAM_END (SRAM_ADDR + SRAM_SIZE)
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#define SDRAM_END (SDRAM_ADDR + SDRAM_SIZE)
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void __init mach_reserve_bootmem ()
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{
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if (SDRAM_ADDR < RAM_END && SDRAM_ADDR > RAM_START)
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/* We can't use the space between SRAM and SDRAM, so
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prevent the kernel from trying. */
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reserve_bootmem(SRAM_END, SDRAM_ADDR - SRAM_END,
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BOOTMEM_DEFAULT);
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}
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void mach_gettimeofday (struct timespec *tv)
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{
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tv->tv_sec = 0;
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tv->tv_nsec = 0;
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}
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void __init mach_sched_init (struct irqaction *timer_action)
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{
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/* Start hardware timer. */
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v850e_timer_d_configure (0, HZ);
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/* Install timer interrupt handler. */
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setup_irq (IRQ_INTCMD(0), timer_action);
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}
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static struct v850e_intc_irq_init irq_inits[] = {
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{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
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{ "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },
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{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
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{ "SRE", IRQ_INTSRE(0), IRQ_INTSRE_NUM, 3, 3 },
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{ "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 3, 4 },
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{ "ST", IRQ_INTST(0), IRQ_INTST_NUM, 3, 5 },
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{ 0 }
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};
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#define NUM_IRQ_INITS (ARRAY_SIZE(irq_inits) - 1)
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static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
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void __init mach_init_irqs (void)
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{
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v850e_intc_init_irq_types (irq_inits, hw_itypes);
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}
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void machine_restart (char *__unused)
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{
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#ifdef CONFIG_RESET_GUARD
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disable_reset_guard ();
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#endif
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asm ("jmp r0"); /* Jump to the reset vector. */
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}
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void machine_halt (void)
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{
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#ifdef CONFIG_RESET_GUARD
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disable_reset_guard ();
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#endif
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local_irq_disable (); /* Ignore all interrupts. */
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AS85EP1_PORT_IO (LEDS_PORT) = 0xAA; /* Note that we halted. */
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for (;;)
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asm ("halt; nop; nop; nop; nop; nop");
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}
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void machine_power_off (void)
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{
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machine_halt ();
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}
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/* Called before configuring an on-chip UART. */
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void as85ep1_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)
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{
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/* Make the shared uart/port pins be uart pins. */
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AS85EP1_PORT_PMC(3) |= (0x5 << chan);
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/* The AS85EP1 connects some general-purpose I/O pins on the CPU to
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the RTS/CTS lines of UART 1's serial connection. I/O pins P53
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and P54 are RTS and CTS respectively. */
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if (chan == 1) {
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/* Put P53 & P54 in I/O port mode. */
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AS85EP1_PORT_PMC(5) &= ~0x18;
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/* Make P53 an output, and P54 an input. */
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AS85EP1_PORT_PM(5) |= 0x10;
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}
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}
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/* Minimum and maximum bounds for the moving upper LED boundary in the
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clock tick display. */
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#define MIN_MAX_POS 0
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#define MAX_MAX_POS 7
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/* There are MAX_MAX_POS^2 - MIN_MAX_POS^2 cycles in the animation, so if
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we pick 6 and 0 as above, we get 49 cycles, which is when divided into
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the standard 100 value for HZ, gives us an almost 1s total time. */
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#define TICKS_PER_FRAME \
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(HZ / (MAX_MAX_POS * MAX_MAX_POS - MIN_MAX_POS * MIN_MAX_POS))
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static void as85ep1_led_tick ()
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{
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static unsigned counter = 0;
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if (++counter == TICKS_PER_FRAME) {
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static int pos = 0, max_pos = MAX_MAX_POS, dir = 1;
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if (dir > 0 && pos == max_pos) {
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dir = -1;
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if (max_pos == MIN_MAX_POS)
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max_pos = MAX_MAX_POS;
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else
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max_pos--;
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} else {
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if (dir < 0 && pos == 0)
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dir = 1;
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if (pos + dir <= max_pos) {
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/* Each bit of port 0 has a LED. */
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set_bit (pos, &AS85EP1_PORT_IO(LEDS_PORT));
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pos += dir;
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clear_bit (pos, &AS85EP1_PORT_IO(LEDS_PORT));
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}
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}
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counter = 0;
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}
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}
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