145 lines
3.9 KiB
C
145 lines
3.9 KiB
C
/*
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* Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/i8259.h>
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#include <asm/mipsregs.h>
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#include <asm/mips-boards/bonito64.h>
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/*
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* the first level int-handler will jump here if it is a bonito irq
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*/
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static void bonito_irqdispatch(void)
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{
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u32 int_status;
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int i;
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/* workaround the IO dma problem: let cpu looping to allow DMA finish */
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int_status = BONITO_INTISR;
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if (int_status & (1 << 10)) {
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while (int_status & (1 << 10)) {
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udelay(1);
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int_status = BONITO_INTISR;
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}
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}
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/* Get pending sources, masked by current enables */
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int_status = BONITO_INTISR & BONITO_INTEN;
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if (int_status != 0) {
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i = __ffs(int_status);
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int_status &= ~(1 << i);
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do_IRQ(BONITO_IRQ_BASE + i);
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}
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}
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static void i8259_irqdispatch(void)
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{
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int irq;
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irq = i8259_irq();
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if (irq >= 0) {
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do_IRQ(irq);
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} else {
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spurious_interrupt();
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}
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
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if (pending & CAUSEF_IP7) {
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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} else if (pending & CAUSEF_IP5) {
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i8259_irqdispatch();
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} else if (pending & CAUSEF_IP2) {
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bonito_irqdispatch();
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} else {
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spurious_interrupt();
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}
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}
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static struct irqaction cascade_irqaction = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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void __init arch_init_irq(void)
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{
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extern void bonito_irq_init(void);
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/*
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* Clear all of the interrupts while we change the able around a bit.
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* int-handler is not on bootstrap
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*/
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clear_c0_status(ST0_IM | ST0_BEV);
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local_irq_disable();
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/* most bonito irq should be level triggered */
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BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
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BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
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BONITO_INTSTEER = 0;
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/*
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* Mask out all interrupt by writing "1" to all bit position in
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* the interrupt reset reg.
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*/
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BONITO_INTENCLR = ~0;
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/* init all controller
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* 0-15 ------> i8259 interrupt
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* 16-23 ------> mips cpu interrupt
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* 32-63 ------> bonito irq
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*/
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/* Sets the first-level interrupt dispatcher. */
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mips_cpu_irq_init();
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init_i8259_irqs();
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bonito_irq_init();
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/*
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printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE);
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printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n",
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BONITO_INTEN, BONITO_INTENSET,
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BONITO_INTENCLR, BONITO_INTISR);
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*/
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/* bonito irq at IP2 */
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
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/* 8259 irq at IP5 */
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setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
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}
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