270 lines
6.7 KiB
C
270 lines
6.7 KiB
C
/*
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* drivers/mtd/nand/sharpsl.c
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*
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* Copyright (C) 2004 Richard Purdie
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*
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* $Id: sharpsl.c,v 1.7 2005/11/07 11:14:31 gleixner Exp $
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*
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* Based on Sharp's NAND driver sharp_sl.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/genhd.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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static void __iomem *sharpsl_io_base;
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static int sharpsl_phys_base = 0x0C000000;
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/* register offset */
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#define ECCLPLB sharpsl_io_base+0x00 /* line parity 7 - 0 bit */
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#define ECCLPUB sharpsl_io_base+0x04 /* line parity 15 - 8 bit */
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#define ECCCP sharpsl_io_base+0x08 /* column parity 5 - 0 bit */
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#define ECCCNTR sharpsl_io_base+0x0C /* ECC byte counter */
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#define ECCCLRR sharpsl_io_base+0x10 /* cleare ECC */
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#define FLASHIO sharpsl_io_base+0x14 /* Flash I/O */
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#define FLASHCTL sharpsl_io_base+0x18 /* Flash Control */
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/* Flash control bit */
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#define FLRYBY (1 << 5)
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#define FLCE1 (1 << 4)
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#define FLWP (1 << 3)
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#define FLALE (1 << 2)
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#define FLCLE (1 << 1)
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#define FLCE0 (1 << 0)
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/*
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* MTD structure for SharpSL
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*/
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static struct mtd_info *sharpsl_mtd = NULL;
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/*
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* Define partitions for flash device
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*/
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#define DEFAULT_NUM_PARTITIONS 3
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static int nr_partitions;
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static struct mtd_partition sharpsl_nand_default_partition_info[] = {
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{
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.name = "System Area",
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.offset = 0,
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.size = 7 * 1024 * 1024,
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},
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{
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.name = "Root Filesystem",
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.offset = 7 * 1024 * 1024,
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.size = 30 * 1024 * 1024,
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},
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{
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.name = "Home Filesystem",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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/*
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* hardware specific access to control-lines
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* ctrl:
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* NAND_CNE: bit 0 -> ! bit 0 & 4
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* NAND_CLE: bit 1 -> bit 1
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* NAND_ALE: bit 2 -> bit 2
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*
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*/
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static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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unsigned char bits = ctrl & 0x07;
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bits |= (ctrl & 0x01) << 4;
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bits ^= 0x11;
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writeb((readb(FLASHCTL) & ~0x17) | bits, FLASHCTL);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, chip->IO_ADDR_W);
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}
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static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
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static struct nand_bbt_descr sharpsl_bbt = {
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.options = 0,
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.offs = 4,
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.len = 2,
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.pattern = scan_ff_pattern
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};
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static struct nand_bbt_descr sharpsl_akita_bbt = {
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.options = 0,
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.offs = 4,
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.len = 1,
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.pattern = scan_ff_pattern
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};
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static struct nand_ecclayout akita_oobinfo = {
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.eccbytes = 24,
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.eccpos = {
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0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
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0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
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0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
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.oobfree = {{0x08, 0x09}}
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};
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static int sharpsl_nand_dev_ready(struct mtd_info *mtd)
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{
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return !((readb(FLASHCTL) & FLRYBY) == 0);
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}
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static void sharpsl_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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writeb(0, ECCCLRR);
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}
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static int sharpsl_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code)
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{
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ecc_code[0] = ~readb(ECCLPUB);
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ecc_code[1] = ~readb(ECCLPLB);
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ecc_code[2] = (~readb(ECCCP) << 2) | 0x03;
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return readb(ECCCNTR) != 0;
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}
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#ifdef CONFIG_MTD_PARTITIONS
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const char *part_probes[] = { "cmdlinepart", NULL };
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#endif
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/*
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* Main initialization routine
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*/
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static int __init sharpsl_nand_init(void)
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{
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struct nand_chip *this;
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struct mtd_partition *sharpsl_partition_info;
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int err = 0;
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/* Allocate memory for MTD device structure and private data */
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sharpsl_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
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if (!sharpsl_mtd) {
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printk("Unable to allocate SharpSL NAND MTD device structure.\n");
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return -ENOMEM;
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}
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/* map physical adress */
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sharpsl_io_base = ioremap(sharpsl_phys_base, 0x1000);
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if (!sharpsl_io_base) {
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printk("ioremap to access Sharp SL NAND chip failed\n");
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kfree(sharpsl_mtd);
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return -EIO;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *)(&sharpsl_mtd[1]);
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/* Initialize structures */
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memset(sharpsl_mtd, 0, sizeof(struct mtd_info));
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memset(this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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sharpsl_mtd->priv = this;
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sharpsl_mtd->owner = THIS_MODULE;
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/*
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* PXA initialize
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*/
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writeb(readb(FLASHCTL) | FLWP, FLASHCTL);
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/* Set address of NAND IO lines */
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this->IO_ADDR_R = FLASHIO;
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this->IO_ADDR_W = FLASHIO;
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/* Set address of hardware control function */
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this->cmd_ctrl = sharpsl_nand_hwcontrol;
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this->dev_ready = sharpsl_nand_dev_ready;
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/* 15 us command delay time */
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this->chip_delay = 15;
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/* set eccmode using hardware ECC */
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this->ecc.mode = NAND_ECC_HW;
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this->ecc.size = 256;
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this->ecc.bytes = 3;
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this->badblock_pattern = &sharpsl_bbt;
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if (machine_is_akita() || machine_is_borzoi()) {
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this->badblock_pattern = &sharpsl_akita_bbt;
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this->ecc.layout = &akita_oobinfo;
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}
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this->ecc.hwctl = sharpsl_nand_enable_hwecc;
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this->ecc.calculate = sharpsl_nand_calculate_ecc;
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this->ecc.correct = nand_correct_data;
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/* Scan to find existence of the device */
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err = nand_scan(sharpsl_mtd, 1);
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if (err) {
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iounmap(sharpsl_io_base);
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kfree(sharpsl_mtd);
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return err;
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}
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/* Register the partitions */
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sharpsl_mtd->name = "sharpsl-nand";
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nr_partitions = parse_mtd_partitions(sharpsl_mtd, part_probes, &sharpsl_partition_info, 0);
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if (nr_partitions <= 0) {
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nr_partitions = DEFAULT_NUM_PARTITIONS;
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sharpsl_partition_info = sharpsl_nand_default_partition_info;
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if (machine_is_poodle()) {
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sharpsl_partition_info[1].size = 22 * 1024 * 1024;
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} else if (machine_is_corgi() || machine_is_shepherd()) {
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sharpsl_partition_info[1].size = 25 * 1024 * 1024;
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} else if (machine_is_husky()) {
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sharpsl_partition_info[1].size = 53 * 1024 * 1024;
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} else if (machine_is_spitz()) {
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sharpsl_partition_info[1].size = 5 * 1024 * 1024;
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} else if (machine_is_akita()) {
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sharpsl_partition_info[1].size = 58 * 1024 * 1024;
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} else if (machine_is_borzoi()) {
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sharpsl_partition_info[1].size = 32 * 1024 * 1024;
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}
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}
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add_mtd_partitions(sharpsl_mtd, sharpsl_partition_info, nr_partitions);
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/* Return happy */
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return 0;
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}
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module_init(sharpsl_nand_init);
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/*
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* Clean up routine
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*/
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static void __exit sharpsl_nand_cleanup(void)
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{
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/* Release resources, unregister device */
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nand_release(sharpsl_mtd);
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iounmap(sharpsl_io_base);
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/* Free the MTD device structure */
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kfree(sharpsl_mtd);
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}
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module_exit(sharpsl_nand_cleanup);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
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MODULE_DESCRIPTION("Device specific logic for NAND flash on Sharp SL-C7xx Series");
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