91 lines
2.8 KiB
C
91 lines
2.8 KiB
C
/* arch/arm/mach-msm/include/mach/irqs.h
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_ARCH_MSM_IRQS_H
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#define __ASM_ARCH_MSM_IRQS_H
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/* MSM ARM11 Interrupt Numbers */
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/* See 80-VE113-1 A, pp219-221 */
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#define INT_A9_M2A_0 0
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#define INT_A9_M2A_1 1
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#define INT_A9_M2A_2 2
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#define INT_A9_M2A_3 3
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#define INT_A9_M2A_4 4
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#define INT_A9_M2A_5 5
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#define INT_A9_M2A_6 6
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#define INT_GP_TIMER_EXP 7
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#define INT_DEBUG_TIMER_EXP 8
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#define INT_UART1 9
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#define INT_UART2 10
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#define INT_UART3 11
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#define INT_UART1_RX 12
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#define INT_UART2_RX 13
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#define INT_UART3_RX 14
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#define INT_USB_OTG 15
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#define INT_MDDI_PRI 16
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#define INT_MDDI_EXT 17
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#define INT_MDDI_CLIENT 18
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#define INT_MDP 19
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#define INT_GRAPHICS 20
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#define INT_ADM_AARM 21
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#define INT_ADSP_A11 22
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#define INT_ADSP_A9_A11 23
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#define INT_SDC1_0 24
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#define INT_SDC1_1 25
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#define INT_SDC2_0 26
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#define INT_SDC2_1 27
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#define INT_KEYSENSE 28
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#define INT_TCHSCRN_SSBI 29
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#define INT_TCHSCRN1 30
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#define INT_TCHSCRN2 31
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#define INT_GPIO_GROUP1 (32 + 0)
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#define INT_GPIO_GROUP2 (32 + 1)
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#define INT_PWB_I2C (32 + 2)
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#define INT_SOFTRESET (32 + 3)
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#define INT_NAND_WR_ER_DONE (32 + 4)
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#define INT_NAND_OP_DONE (32 + 5)
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#define INT_PBUS_ARM11 (32 + 6)
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#define INT_AXI_MPU_SMI (32 + 7)
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#define INT_AXI_MPU_EBI1 (32 + 8)
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#define INT_AD_HSSD (32 + 9)
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#define INT_ARM11_PMU (32 + 10)
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#define INT_ARM11_DMA (32 + 11)
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#define INT_TSIF_IRQ (32 + 12)
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#define INT_UART1DM_IRQ (32 + 13)
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#define INT_UART1DM_RX (32 + 14)
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#define INT_USB_HS (32 + 15)
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#define INT_SDC3_0 (32 + 16)
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#define INT_SDC3_1 (32 + 17)
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#define INT_SDC4_0 (32 + 18)
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#define INT_SDC4_1 (32 + 19)
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#define INT_UART2DM_RX (32 + 20)
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#define INT_UART2DM_IRQ (32 + 21)
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/* 22-31 are reserved */
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#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
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#define NR_MSM_IRQS 64
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#define NR_GPIO_IRQS 122
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#define NR_BOARD_IRQS 64
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#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
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#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
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#endif
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