264 lines
8.3 KiB
C
264 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* sl28cpld PWM driver
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*
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* Copyright (c) 2020 Michael Walle <michael@walle.cc>
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*
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* There is no public datasheet available for this PWM core. But it is easy
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* enough to be briefly explained. It consists of one 8-bit counter. The PWM
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* supports four distinct frequencies by selecting when to reset the counter.
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* With the prescaler setting you can select which bit of the counter is used
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* to reset it. This implies that the higher the frequency the less remaining
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* bits are available for the actual counter.
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*
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* Let cnt[7:0] be the counter, clocked at 32kHz:
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* +-----------+--------+--------------+-----------+---------------+
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* | prescaler | reset | counter bits | frequency | period length |
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* +-----------+--------+--------------+-----------+---------------+
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* | 0 | cnt[7] | cnt[6:0] | 250 Hz | 4000000 ns |
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* | 1 | cnt[6] | cnt[5:0] | 500 Hz | 2000000 ns |
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* | 2 | cnt[5] | cnt[4:0] | 1 kHz | 1000000 ns |
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* | 3 | cnt[4] | cnt[3:0] | 2 kHz | 500000 ns |
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* +-----------+--------+--------------+-----------+---------------+
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*
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* Limitations:
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* - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
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* - The hardware cannot atomically set the prescaler and the counter value,
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* which might lead to glitches and inconsistent states if a write fails.
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* - The counter is not reset if you switch the prescaler which leads
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* to glitches, too.
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* - The duty cycle will switch immediately and not after a complete cycle.
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* - Depending on the actual implementation, disabling the PWM might have
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* side effects. For example, if the output pin is shared with a GPIO pin
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* it will automatically switch back to GPIO mode.
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*/
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#include <linux/bitfield.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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/*
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* PWM timer block registers.
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*/
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#define SL28CPLD_PWM_CTRL 0x00
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#define SL28CPLD_PWM_CTRL_ENABLE BIT(7)
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#define SL28CPLD_PWM_CTRL_PRESCALER_MASK GENMASK(1, 0)
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#define SL28CPLD_PWM_CYCLE 0x01
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#define SL28CPLD_PWM_CYCLE_MAX GENMASK(6, 0)
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#define SL28CPLD_PWM_CLK 32000 /* 32 kHz */
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#define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler) (1 << (7 - (prescaler)))
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#define SL28CPLD_PWM_PERIOD(prescaler) \
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(NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler))
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/*
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* We calculate the duty cycle like this:
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* duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle
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*
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* With
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* max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
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* max_duty_cycle = 1 << (7 - prescaler)
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* this then simplifies to:
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* duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC
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* = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg
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*
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* NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing
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* precision by doing the divison first.
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*/
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#define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) \
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(NSEC_PER_SEC / SL28CPLD_PWM_CLK * (reg))
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#define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) \
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(DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK))
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#define sl28cpld_pwm_read(priv, reg, val) \
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regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
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#define sl28cpld_pwm_write(priv, reg, val) \
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regmap_write((priv)->regmap, (priv)->offset + (reg), (val))
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struct sl28cpld_pwm {
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struct pwm_chip pwm_chip;
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struct regmap *regmap;
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u32 offset;
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};
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#define sl28cpld_pwm_from_chip(_chip) \
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container_of(_chip, struct sl28cpld_pwm, pwm_chip)
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static int sl28cpld_pwm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
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unsigned int reg;
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int prescaler;
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sl28cpld_pwm_read(priv, SL28CPLD_PWM_CTRL, ®);
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state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;
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prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg);
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state->period = SL28CPLD_PWM_PERIOD(prescaler);
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sl28cpld_pwm_read(priv, SL28CPLD_PWM_CYCLE, ®);
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state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);
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state->polarity = PWM_POLARITY_NORMAL;
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/*
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* Sanitize values for the PWM core. Depending on the prescaler it
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* might happen that we calculate a duty_cycle greater than the actual
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* period. This might happen if someone (e.g. the bootloader) sets an
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* invalid combination of values. The behavior of the hardware is
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* undefined in this case. But we need to report sane values back to
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* the PWM core.
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*/
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state->duty_cycle = min(state->duty_cycle, state->period);
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return 0;
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}
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static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
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unsigned int cycle, prescaler;
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bool write_duty_cycle_first;
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int ret;
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u8 ctrl;
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/* Polarity inversion is not supported */
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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/*
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* Calculate the prescaler. Pick the biggest period that isn't
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* bigger than the requested period.
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*/
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prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);
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prescaler = order_base_2(prescaler);
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if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK))
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return -ERANGE;
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ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler);
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if (state->enabled)
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ctrl |= SL28CPLD_PWM_CTRL_ENABLE;
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cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);
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cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler));
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/*
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* Work around the hardware limitation. See also above. Trap 100% duty
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* cycle if the prescaler is 0. Set prescaler to 1 instead. We don't
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* care about the frequency because its "all-one" in either case.
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*
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* We don't need to check the actual prescaler setting, because only
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* if the prescaler is 0 we can have this particular value.
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*/
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if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) {
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ctrl &= ~SL28CPLD_PWM_CTRL_PRESCALER_MASK;
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ctrl |= FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, 1);
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cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1);
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}
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/*
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* To avoid glitches when we switch the prescaler, we have to make sure
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* we have a valid duty cycle for the new mode.
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*
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* Take the current prescaler (or the current period length) into
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* account to decide whether we have to write the duty cycle or the new
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* prescaler first. If the period length is decreasing we have to
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* write the duty cycle first.
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*/
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write_duty_cycle_first = pwm->state.period > state->period;
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if (write_duty_cycle_first) {
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ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
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if (ret)
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return ret;
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}
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ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CTRL, ctrl);
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if (ret)
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return ret;
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if (!write_duty_cycle_first) {
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ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct pwm_ops sl28cpld_pwm_ops = {
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.apply = sl28cpld_pwm_apply,
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.get_state = sl28cpld_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static int sl28cpld_pwm_probe(struct platform_device *pdev)
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{
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struct sl28cpld_pwm *priv;
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struct pwm_chip *chip;
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int ret;
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if (!pdev->dev.parent) {
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dev_err(&pdev->dev, "no parent device\n");
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return -ENODEV;
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}
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!priv->regmap) {
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dev_err(&pdev->dev, "could not get parent regmap\n");
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return -ENODEV;
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}
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ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);
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if (ret) {
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dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",
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ERR_PTR(ret));
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return -EINVAL;
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}
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/* Initialize the pwm_chip structure */
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chip = &priv->pwm_chip;
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chip->dev = &pdev->dev;
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chip->ops = &sl28cpld_pwm_ops;
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chip->npwm = 1;
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ret = devm_pwmchip_add(&pdev->dev, &priv->pwm_chip);
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if (ret) {
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dev_err(&pdev->dev, "failed to add PWM chip (%pe)",
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ERR_PTR(ret));
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return ret;
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}
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return 0;
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}
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static const struct of_device_id sl28cpld_pwm_of_match[] = {
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{ .compatible = "kontron,sl28cpld-pwm" },
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{}
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};
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MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match);
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static struct platform_driver sl28cpld_pwm_driver = {
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.probe = sl28cpld_pwm_probe,
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.driver = {
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.name = "sl28cpld-pwm",
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.of_match_table = sl28cpld_pwm_of_match,
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},
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};
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module_platform_driver(sl28cpld_pwm_driver);
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MODULE_DESCRIPTION("sl28cpld PWM Driver");
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MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
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MODULE_LICENSE("GPL");
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