acrn-kernel/drivers/perf
Robin Murphy f81be7edb7 Partially revert "perf/arm-cmn: Optimise DTC counter accesses"
[ Upstream commit a428eb4b99 ]

It turns out the optimisation implemented by commit 4f2c3872dd is
totally broken, since all the places that consume hw->dtcs_used for
events other than cycle count are still not expecting it to be sparsely
populated, and fail to read all the relevant DTC counters correctly if
so.

If implemented correctly, the optimisation potentially saves up to 3
register reads per event update, which is reasonably significant for
events targeting a single node, but still not worth a massive amount of
additional code complexity overall. Getting it right within the current
design looks a fair bit more involved than it was ever intended to be,
so let's just make a functional revert which restores the old behaviour
while still backporting easily.

Fixes: 4f2c3872dd ("perf/arm-cmn: Optimise DTC counter accesses")
Reported-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/b41bb4ed7283c3d8400ce5cf5e6ec94915e6750f.1674498637.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-02-01 08:34:49 +01:00
..
hisilicon
Kconfig
Makefile
alibaba_uncore_drw_pmu.c
apple_m1_cpu_pmu.c
arm-cci.c
arm-ccn.c
arm-cmn.c
arm_dmc620_pmu.c
arm_dsu_pmu.c
arm_pmu.c
arm_pmu_acpi.c
arm_pmu_platform.c
arm_smmuv3_pmu.c
arm_spe_pmu.c
fsl_imx8_ddr_perf.c
marvell_cn10k_ddr_pmu.c
marvell_cn10k_tad_pmu.c
qcom_l2_pmu.c
qcom_l3_pmu.c
riscv_pmu.c
riscv_pmu_legacy.c
riscv_pmu_sbi.c
thunderx2_pmu.c
xgene_pmu.c