149 lines
5.2 KiB
C
149 lines
5.2 KiB
C
/*
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* arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
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*
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* Copyright (C) 2006,2007 by Digi International Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGSSYSNS9360_H
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#define __ASM_ARCH_REGSSYSNS9360_H
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#include <mach/hardware.h>
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/* System Control Module */
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/* AHB Arbiter Gen Configuration */
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#define SYS_AHBAGENCONF __REG(0xa0900000)
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/* BRC */
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#define SYS_BRC(x) __REG2(0xa0900004, (x))
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/* Timer x Reload Count register */
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#define SYS_TRC(x) __REG2(0xa0900044, (x))
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/* Timer x Read register */
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#define SYS_TR(x) __REG2(0xa0900084, (x))
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/* Timer Interrupt Status register */
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#define SYS_TIS __REG(0xa0900170)
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/* PLL Configuration register */
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#define SYS_PLL __REG(0xa0900188)
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/* PLL FS status */
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#define SYS_PLL_FS __REGBITS(24, 23)
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/* PLL ND status */
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#define SYS_PLL_ND __REGBITS(20, 16)
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/* PLL Configuration register: PLL SW change */
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#define SYS_PLL_SWC __REGBIT(15)
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#define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0)
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#define SYS_PLL_SWC_YES __REGVAL(SYS_PLL_SWC, 1)
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/* Timer x Control register */
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#define SYS_TC(x) __REG2(0xa0900190, (x))
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/* Timer x Control register: Timer enable */
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#define SYS_TCx_TEN __REGBIT(15)
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#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0)
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#define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1)
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/* Timer x Control register: CPU debug mode */
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#define SYS_TCx_TDBG __REGBIT(10)
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#define SYS_TCx_TDBG_CONT __REGVAL(SYS_TCx_TDBG, 0)
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#define SYS_TCx_TDBG_STOP __REGVAL(SYS_TCx_TDBG, 1)
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/* Timer x Control register: Interrupt clear */
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#define SYS_TCx_INTC __REGBIT(9)
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#define SYS_TCx_INTC_UNSET __REGVAL(SYS_TCx_INTC, 0)
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#define SYS_TCx_INTC_SET __REGVAL(SYS_TCx_INTC, 1)
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/* Timer x Control register: Timer clock select */
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#define SYS_TCx_TLCS __REGBITS(8, 6)
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#define SYS_TCx_TLCS_CPU __REGVAL(SYS_TCx_TLCS, 0) /* CPU clock */
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#define SYS_TCx_TLCS_DIV2 __REGVAL(SYS_TCx_TLCS, 1) /* CPU clock / 2 */
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#define SYS_TCx_TLCS_DIV4 __REGVAL(SYS_TCx_TLCS, 2) /* CPU clock / 4 */
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#define SYS_TCx_TLCS_DIV8 __REGVAL(SYS_TCx_TLCS, 3) /* CPU clock / 8 */
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#define SYS_TCx_TLCS_DIV16 __REGVAL(SYS_TCx_TLCS, 4) /* CPU clock / 16 */
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#define SYS_TCx_TLCS_DIV32 __REGVAL(SYS_TCx_TLCS, 5) /* CPU clock / 32 */
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#define SYS_TCx_TLCS_DIV64 __REGVAL(SYS_TCx_TLCS, 6) /* CPU clock / 64 */
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#define SYS_TCx_TLCS_EXT __REGVAL(SYS_TCx_TLCS, 7)
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/* Timer x Control register: Timer mode */
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#define SYS_TCx_TM __REGBITS(5, 4)
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#define SYS_TCx_TM_IEE __REGVAL(SYS_TCx_TM, 0) /* Internal timer or external event */
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#define SYS_TCx_TM_ELL __REGVAL(SYS_TCx_TM, 1) /* External low-level, gated timer */
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#define SYS_TCx_TM_EHL __REGVAL(SYS_TCx_TM, 2) /* External high-level, gated timer */
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#define SYS_TCx_TM_CONCAT __REGVAL(SYS_TCx_TM, 3) /* Concatenate the lower timer. */
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/* Timer x Control register: Interrupt select */
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#define SYS_TCx_INTS __REGBIT(3)
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#define SYS_TCx_INTS_DIS __REGVAL(SYS_TCx_INTS, 0)
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#define SYS_TCx_INTS_EN __REGVAL(SYS_TCx_INTS, 1)
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/* Timer x Control register: Up/down select */
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#define SYS_TCx_UDS __REGBIT(2)
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#define SYS_TCx_UDS_UP __REGVAL(SYS_TCx_UDS, 0)
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#define SYS_TCx_UDS_DOWN __REGVAL(SYS_TCx_UDS, 1)
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/* Timer x Control register: 32- or 16-bit timer */
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#define SYS_TCx_TSZ __REGBIT(1)
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#define SYS_TCx_TSZ_16 __REGVAL(SYS_TCx_TSZ, 0)
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#define SYS_TCx_TSZ_32 __REGVAL(SYS_TCx_TSZ, 1)
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/* Timer x Control register: Reload enable */
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#define SYS_TCx_REN __REGBIT(0)
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#define SYS_TCx_REN_DIS __REGVAL(SYS_TCx_REN, 0)
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#define SYS_TCx_REN_EN __REGVAL(SYS_TCx_REN, 1)
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/* System Memory Chip Select x Dynamic Memory Base */
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#define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1)
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/* System Memory Chip Select x Dynamic Memory Mask */
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#define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1)
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/* System Memory Chip Select x Static Memory Base */
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#define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1)
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/* System Memory Chip Select x Static Memory Base: Chip select x base */
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#define SYS_SMCSSMB_CSxB __REGBITS(31, 12)
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/* System Memory Chip Select x Static Memory Mask */
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#define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1)
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/* System Memory Chip Select x Static Memory Mask: Chip select x mask */
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#define SYS_SMCSSMM_CSxM __REGBITS(31, 12)
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/* System Memory Chip Select x Static Memory Mask: Chip select x enable */
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#define SYS_SMCSSMM_CSEx __REGBIT(0)
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#define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0)
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#define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1)
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/* General purpose, user-defined ID register */
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#define SYS_GENID __REG(0xa0900210)
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/* External Interrupt x Control register */
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#define SYS_EIC(x) __REG2(0xa0900214, (x))
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/* External Interrupt x Control register: Status */
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#define SYS_EIC_STS __REGBIT(3)
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/* External Interrupt x Control register: Clear */
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#define SYS_EIC_CLR __REGBIT(2)
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/* External Interrupt x Control register: Polarity */
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#define SYS_EIC_PLTY __REGBIT(1)
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#define SYS_EIC_PLTY_AH __REGVAL(SYS_EIC_PLTY, 0)
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#define SYS_EIC_PLTY_AL __REGVAL(SYS_EIC_PLTY, 1)
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/* External Interrupt x Control register: Level edge */
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#define SYS_EIC_LVEDG __REGBIT(0)
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#define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0)
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#define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1)
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#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */
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