73 lines
1.6 KiB
C
73 lines
1.6 KiB
C
/*
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* xtensa mmu stuff
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*
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* Extracted from init.c
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*/
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#include <linux/percpu.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/cache.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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void __init paging_init(void)
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{
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memset(swapper_pg_dir, 0, PAGE_SIZE);
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}
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/*
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* Flush the mmu and reset associated register to default values.
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*/
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void __init init_mmu(void)
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{
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#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
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/*
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* Writing zeros to the instruction and data TLBCFG special
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* registers ensure that valid values exist in the register.
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*
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* For existing PGSZID<w> fields, zero selects the first element
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* of the page-size array. For nonexistent PGSZID<w> fields,
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* zero is the best value to write. Also, when changing PGSZID<w>
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* fields, the corresponding TLB must be flushed.
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*/
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set_itlbcfg_register(0);
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set_dtlbcfg_register(0);
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#endif
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flush_tlb_all();
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/* Set rasid register to a known value. */
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set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
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/* Set PTEVADDR special register to the start of the page
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* table, which is in kernel mappable space (ie. not
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* statically mapped). This register's value is undefined on
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* reset.
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*/
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set_ptevaddr_register(PGTABLE_START);
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}
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struct kmem_cache *pgtable_cache __read_mostly;
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static void pgd_ctor(void *addr)
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{
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pte_t *ptep = (pte_t *)addr;
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int i;
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for (i = 0; i < 1024; i++, ptep++)
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pte_clear(NULL, 0, ptep);
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}
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void __init pgtable_cache_init(void)
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{
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pgtable_cache = kmem_cache_create("pgd",
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PAGE_SIZE, PAGE_SIZE,
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SLAB_HWCACHE_ALIGN,
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pgd_ctor);
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}
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