180 lines
2.7 KiB
ArmAsm
180 lines
2.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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*
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* Copyright (C) IBM Corporation, 2012
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*
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* Author: Anton Blanchard <anton@au.ibm.com>
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*/
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#include <asm/ppc_asm.h>
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#include <asm/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/export.h>
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/**
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* __arch_clear_user: - Zero a block of memory in user space, with less checking.
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* @to: Destination address, in user space.
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* @n: Number of bytes to zero.
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*
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* Zero a block of memory in user space. Caller must check
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* the specified block with access_ok() before calling this function.
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*
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* Returns number of bytes that could not be cleared.
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* On success, this will be zero.
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*/
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.macro err1
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100:
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EX_TABLE(100b,.Ldo_err1)
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.endm
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.macro err2
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200:
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EX_TABLE(200b,.Ldo_err2)
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.endm
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.macro err3
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300:
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EX_TABLE(300b,.Ldo_err3)
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.endm
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.Ldo_err1:
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mr r3,r8
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.Ldo_err2:
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mtctr r4
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1:
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err3; stb r0,0(r3)
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addi r3,r3,1
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addi r4,r4,-1
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bdnz 1b
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.Ldo_err3:
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mr r3,r4
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blr
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_GLOBAL_TOC(__arch_clear_user)
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cmpdi r4,32
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neg r6,r3
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li r0,0
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blt .Lshort_clear
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mr r8,r3
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mtocrf 0x01,r6
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clrldi r6,r6,(64-3)
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/* Get the destination 8 byte aligned */
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bf cr7*4+3,1f
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err1; stb r0,0(r3)
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addi r3,r3,1
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1: bf cr7*4+2,2f
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err1; sth r0,0(r3)
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addi r3,r3,2
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2: bf cr7*4+1,3f
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err1; stw r0,0(r3)
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addi r3,r3,4
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3: sub r4,r4,r6
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cmpdi r4,32
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cmpdi cr1,r4,512
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blt .Lshort_clear
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bgt cr1,.Llong_clear
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.Lmedium_clear:
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srdi r6,r4,5
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mtctr r6
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/* Do 32 byte chunks */
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4:
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err2; std r0,0(r3)
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err2; std r0,8(r3)
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err2; std r0,16(r3)
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err2; std r0,24(r3)
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addi r3,r3,32
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addi r4,r4,-32
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bdnz 4b
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.Lshort_clear:
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/* up to 31 bytes to go */
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cmpdi r4,16
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blt 6f
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err2; std r0,0(r3)
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err2; std r0,8(r3)
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addi r3,r3,16
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addi r4,r4,-16
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/* Up to 15 bytes to go */
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6: mr r8,r3
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clrldi r4,r4,(64-4)
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mtocrf 0x01,r4
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bf cr7*4+0,7f
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err1; std r0,0(r3)
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addi r3,r3,8
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7: bf cr7*4+1,8f
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err1; stw r0,0(r3)
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addi r3,r3,4
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8: bf cr7*4+2,9f
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err1; sth r0,0(r3)
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addi r3,r3,2
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9: bf cr7*4+3,10f
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err1; stb r0,0(r3)
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10: li r3,0
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blr
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.Llong_clear:
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LOAD_REG_ADDR(r5, ppc64_caches)
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bf cr7*4+0,11f
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err2; std r0,0(r3)
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addi r3,r3,8
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addi r4,r4,-8
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/* Destination is 16 byte aligned, need to get it cache block aligned */
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11: lwz r7,DCACHEL1LOGBLOCKSIZE(r5)
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lwz r9,DCACHEL1BLOCKSIZE(r5)
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/*
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* With worst case alignment the long clear loop takes a minimum
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* of 1 byte less than 2 cachelines.
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*/
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sldi r10,r9,2
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cmpd r4,r10
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blt .Lmedium_clear
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neg r6,r3
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addi r10,r9,-1
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and. r5,r6,r10
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beq 13f
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srdi r6,r5,4
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mtctr r6
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mr r8,r3
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12:
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err1; std r0,0(r3)
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err1; std r0,8(r3)
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addi r3,r3,16
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bdnz 12b
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sub r4,r4,r5
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13: srd r6,r4,r7
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mtctr r6
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mr r8,r3
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14:
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err1; dcbz 0,r3
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add r3,r3,r9
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bdnz 14b
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and r4,r4,r10
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cmpdi r4,32
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blt .Lshort_clear
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b .Lmedium_clear
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EXPORT_SYMBOL(__arch_clear_user)
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