371 lines
8.6 KiB
C
371 lines
8.6 KiB
C
/*
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* Atheros AR71xx/AR724x/AR913x specific interrupt handling
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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static void (*ath79_ip2_handler)(void);
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static void (*ath79_ip3_handler)(void);
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static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *base = ath79_reset_base;
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u32 pending;
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pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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if (!pending) {
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spurious_interrupt();
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return;
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}
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while (pending) {
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int bit = __ffs(pending);
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generic_handle_irq(ATH79_MISC_IRQ(bit));
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pending &= ~BIT(bit);
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}
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}
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static void ar71xx_misc_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
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void __iomem *base = ath79_reset_base;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar71xx_misc_irq_mask(struct irq_data *d)
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{
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unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
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void __iomem *base = ath79_reset_base;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_ack(struct irq_data *d)
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{
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unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
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void __iomem *base = ath79_reset_base;
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u32 t;
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t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
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/* flush write */
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__raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static struct irq_chip ath79_misc_irq_chip = {
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.name = "MISC",
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.irq_unmask = ar71xx_misc_irq_unmask,
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.irq_mask = ar71xx_misc_irq_mask,
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};
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static void __init ath79_misc_irq_init(void)
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{
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void __iomem *base = ath79_reset_base;
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int i;
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
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__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
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if (soc_is_ar71xx() || soc_is_ar913x())
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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else if (soc_is_ar724x() ||
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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soc_is_qca955x())
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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else
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BUG();
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for (i = ATH79_MISC_IRQ_BASE;
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i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
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irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
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handle_level_irq);
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}
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irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
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}
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static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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{
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u32 status;
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disable_irq_nosync(irq);
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status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
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if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
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ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
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generic_handle_irq(ATH79_IP2_IRQ(0));
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} else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
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ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
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generic_handle_irq(ATH79_IP2_IRQ(1));
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} else {
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spurious_interrupt();
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}
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enable_irq(irq);
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}
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static void ar934x_ip2_irq_init(void)
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{
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int i;
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &dummy_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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}
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static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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{
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u32 status;
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disable_irq_nosync(irq);
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status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
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status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
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if (status == 0) {
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spurious_interrupt();
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goto enable;
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}
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if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP2_IRQ(0));
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}
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if (status & QCA955X_EXT_INT_WMAC_ALL) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP2_IRQ(1));
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}
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enable:
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enable_irq(irq);
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}
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static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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{
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u32 status;
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disable_irq_nosync(irq);
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status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
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status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
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QCA955X_EXT_INT_USB1 |
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QCA955X_EXT_INT_USB2;
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if (status == 0) {
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spurious_interrupt();
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goto enable;
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}
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if (status & QCA955X_EXT_INT_USB1) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP3_IRQ(0));
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}
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if (status & QCA955X_EXT_INT_USB2) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP3_IRQ(1));
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}
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if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
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/* TODO: flush DDR? */
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generic_handle_irq(ATH79_IP3_IRQ(2));
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}
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enable:
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enable_irq(irq);
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}
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static void qca955x_irq_init(void)
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{
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int i;
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &dummy_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
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for (i = ATH79_IP3_IRQ_BASE;
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i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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irq_set_chip_and_handler(i, &dummy_irq_chip,
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handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP7)
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do_IRQ(ATH79_CPU_IRQ(7));
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else if (pending & STATUSF_IP2)
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ath79_ip2_handler();
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else if (pending & STATUSF_IP4)
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do_IRQ(ATH79_CPU_IRQ(4));
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else if (pending & STATUSF_IP5)
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do_IRQ(ATH79_CPU_IRQ(5));
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else if (pending & STATUSF_IP3)
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ath79_ip3_handler();
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else if (pending & STATUSF_IP6)
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do_IRQ(ATH79_CPU_IRQ(6));
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else
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spurious_interrupt();
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}
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/*
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* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
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* these devices typically allocate coherent DMA memory, however the
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* DMA controller may still have some unsynchronized data in the FIFO.
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* Issue a flush in the handlers to ensure that the driver sees
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* the update.
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*/
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static void ath79_default_ip2_handler(void)
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{
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do_IRQ(ATH79_CPU_IRQ(2));
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}
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static void ath79_default_ip3_handler(void)
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{
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do_IRQ(ATH79_CPU_IRQ(3));
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}
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static void ar71xx_ip2_handler(void)
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{
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ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
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do_IRQ(ATH79_CPU_IRQ(2));
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}
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static void ar724x_ip2_handler(void)
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{
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ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
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do_IRQ(ATH79_CPU_IRQ(2));
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}
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static void ar913x_ip2_handler(void)
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{
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ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
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do_IRQ(ATH79_CPU_IRQ(2));
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}
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static void ar933x_ip2_handler(void)
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{
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ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
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do_IRQ(ATH79_CPU_IRQ(2));
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}
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static void ar71xx_ip3_handler(void)
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{
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ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
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do_IRQ(ATH79_CPU_IRQ(3));
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}
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static void ar724x_ip3_handler(void)
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{
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ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
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do_IRQ(ATH79_CPU_IRQ(3));
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}
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static void ar913x_ip3_handler(void)
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{
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ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
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do_IRQ(ATH79_CPU_IRQ(3));
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}
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static void ar933x_ip3_handler(void)
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{
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ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
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do_IRQ(ATH79_CPU_IRQ(3));
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}
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static void ar934x_ip3_handler(void)
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{
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ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
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do_IRQ(ATH79_CPU_IRQ(3));
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}
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void __init arch_init_irq(void)
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{
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if (soc_is_ar71xx()) {
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ath79_ip2_handler = ar71xx_ip2_handler;
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ath79_ip3_handler = ar71xx_ip3_handler;
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} else if (soc_is_ar724x()) {
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ath79_ip2_handler = ar724x_ip2_handler;
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ath79_ip3_handler = ar724x_ip3_handler;
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} else if (soc_is_ar913x()) {
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ath79_ip2_handler = ar913x_ip2_handler;
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ath79_ip3_handler = ar913x_ip3_handler;
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} else if (soc_is_ar933x()) {
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ath79_ip2_handler = ar933x_ip2_handler;
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ath79_ip3_handler = ar933x_ip3_handler;
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} else if (soc_is_ar934x()) {
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ath79_ip2_handler = ath79_default_ip2_handler;
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ath79_ip3_handler = ar934x_ip3_handler;
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} else if (soc_is_qca955x()) {
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ath79_ip2_handler = ath79_default_ip2_handler;
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ath79_ip3_handler = ath79_default_ip3_handler;
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} else {
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BUG();
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}
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cp0_perfcount_irq = ATH79_MISC_IRQ(5);
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mips_cpu_irq_init();
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ath79_misc_irq_init();
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if (soc_is_ar934x())
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ar934x_ip2_irq_init();
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else if (soc_is_qca955x())
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qca955x_irq_init();
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}
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