153 lines
3.3 KiB
C
153 lines
3.3 KiB
C
/*
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* mmp APB clock operation source file
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*
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* Copyright (C) 2012 Marvell
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* Chao Xie <xiechao.mail@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include "clk.h"
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/* Common APB clock register bit definitions */
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#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
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#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
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#define APBC_RST (1 << 2) /* Reset Generation */
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#define APBC_POWER (1 << 7) /* Reset Generation */
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#define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw)
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struct clk_apbc {
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struct clk_hw hw;
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void __iomem *base;
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unsigned int delay;
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unsigned int flags;
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spinlock_t *lock;
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};
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static int clk_apbc_prepare(struct clk_hw *hw)
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{
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struct clk_apbc *apbc = to_clk_apbc(hw);
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unsigned int data;
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unsigned long flags = 0;
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/*
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* It may share same register as MUX clock,
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* and it will impact FNCLK enable. Spinlock is needed
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*/
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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if (apbc->flags & APBC_POWER_CTRL)
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data |= APBC_POWER;
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data |= APBC_FNCLK;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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udelay(apbc->delay);
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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data |= APBC_APBCLK;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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udelay(apbc->delay);
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if (!(apbc->flags & APBC_NO_BUS_CTRL)) {
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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data &= ~APBC_RST;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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}
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return 0;
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}
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static void clk_apbc_unprepare(struct clk_hw *hw)
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{
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struct clk_apbc *apbc = to_clk_apbc(hw);
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unsigned long data;
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unsigned long flags = 0;
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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if (apbc->flags & APBC_POWER_CTRL)
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data &= ~APBC_POWER;
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data &= ~APBC_FNCLK;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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udelay(10);
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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data &= ~APBC_APBCLK;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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}
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struct clk_ops clk_apbc_ops = {
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.prepare = clk_apbc_prepare,
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.unprepare = clk_apbc_unprepare,
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};
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struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name,
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void __iomem *base, unsigned int delay,
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unsigned int apbc_flags, spinlock_t *lock)
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{
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struct clk_apbc *apbc;
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struct clk *clk;
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struct clk_init_data init;
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apbc = kzalloc(sizeof(*apbc), GFP_KERNEL);
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if (!apbc)
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return NULL;
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init.name = name;
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init.ops = &clk_apbc_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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apbc->base = base;
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apbc->delay = delay;
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apbc->flags = apbc_flags;
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apbc->lock = lock;
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apbc->hw.init = &init;
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clk = clk_register(NULL, &apbc->hw);
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if (IS_ERR(clk))
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kfree(apbc);
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return clk;
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}
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