131 lines
2.9 KiB
ArmAsm
131 lines
2.9 KiB
ArmAsm
/*
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* File: arch/blackfin/mach-common/cplbhdlr.S
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* Based on:
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* Author: LG Soft India
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*
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* Created: ?
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* Description: CPLB exception handler
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/linkage.h>
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#include <asm/cplb.h>
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#include <asm/entry.h>
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#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
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.section .l1.text
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#else
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.text
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#endif
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.type _cplb_mgr, STT_FUNC;
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.type _panic_cplb_error, STT_FUNC;
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.align 2
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ENTRY(__cplb_hdr)
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R2 = SEQSTAT;
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/* Mask the contents of SEQSTAT and leave only EXCAUSE in R2 */
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R2 <<= 26;
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R2 >>= 26;
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R1 = 0x23; /* Data access CPLB protection violation */
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CC = R2 == R1;
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IF !CC JUMP .Lnot_data_write;
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R0 = 2; /* is a write to data space*/
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JUMP .Lis_icplb_miss;
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.Lnot_data_write:
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R1 = 0x2C; /* CPLB miss on an instruction fetch */
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CC = R2 == R1;
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R0 = 0; /* is_data_miss == False*/
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IF CC JUMP .Lis_icplb_miss;
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R1 = 0x26;
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CC = R2 == R1;
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IF !CC JUMP .Lunknown;
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R0 = 1; /* is_data_miss == True*/
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.Lis_icplb_miss:
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#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
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# if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE)
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R1 = CPLB_ENABLE_ICACHE;
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# endif
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# if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
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R1 = CPLB_ENABLE_DCACHE;
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# endif
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# if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
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R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
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# endif
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#else
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R1 = 0;
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#endif
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[--SP] = RETS;
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CALL _cplb_mgr;
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RETS = [SP++];
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CC = R0 == 0;
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IF !CC JUMP .Lnot_replaced;
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RTS;
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/*
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* Diagnostic exception handlers
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*/
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.Lunknown:
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R0 = CPLB_UNKNOWN_ERR;
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JUMP .Lcplb_error;
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.Lnot_replaced:
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CC = R0 == CPLB_NO_UNLOCKED;
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IF !CC JUMP .Lnext_check;
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R0 = CPLB_NO_UNLOCKED;
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JUMP .Lcplb_error;
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.Lnext_check:
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CC = R0 == CPLB_NO_ADDR_MATCH;
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IF !CC JUMP .Lnext_check2;
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R0 = CPLB_NO_ADDR_MATCH;
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JUMP .Lcplb_error;
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.Lnext_check2:
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CC = R0 == CPLB_PROT_VIOL;
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IF !CC JUMP .Lstrange_return_from_cplb_mgr;
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R0 = CPLB_PROT_VIOL;
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JUMP .Lcplb_error;
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.Lstrange_return_from_cplb_mgr:
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IDLE;
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CSYNC;
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JUMP .Lstrange_return_from_cplb_mgr;
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.Lcplb_error:
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R1 = sp;
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SP += -12;
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call _panic_cplb_error;
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SP += 12;
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JUMP _handle_bad_cplb;
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ENDPROC(__cplb_hdr)
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