89 lines
3.4 KiB
C
89 lines
3.4 KiB
C
/*
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* MPC85xx/86xx PCI Express structure define
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*
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* Copyright 2007 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifdef __KERNEL__
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#ifndef __POWERPC_FSL_PCI_H
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#define __POWERPC_FSL_PCI_H
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#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
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/* PCI/PCI Express outbound window reg */
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struct pci_outbound_window_regs {
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__be32 potar; /* 0x.0 - Outbound translation address register */
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__be32 potear; /* 0x.4 - Outbound translation extended address register */
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__be32 powbar; /* 0x.8 - Outbound window base address register */
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u8 res1[4];
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__be32 powar; /* 0x.10 - Outbound window attributes register */
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u8 res2[12];
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};
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/* PCI/PCI Express inbound window reg */
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struct pci_inbound_window_regs {
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__be32 pitar; /* 0x.0 - Inbound translation address register */
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u8 res1[4];
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__be32 piwbar; /* 0x.8 - Inbound window base address register */
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__be32 piwbear; /* 0x.c - Inbound window base extended address register */
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__be32 piwar; /* 0x.10 - Inbound window attributes register */
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u8 res2[12];
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};
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/* PCI/PCI Express IO block registers for 85xx/86xx */
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struct ccsr_pci {
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__be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
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__be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
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__be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
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__be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
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__be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
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u8 res2[12];
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__be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
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__be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
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__be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
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__be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
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u8 res3[3024];
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/* PCI/PCI Express outbound window 0-4
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* Window 0 is the default window and is the only window enabled upon reset.
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* The default outbound register set is used when a transaction misses
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* in all of the other outbound windows.
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*/
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struct pci_outbound_window_regs pow[5];
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u8 res14[256];
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/* PCI/PCI Express inbound window 3-1
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* inbound window 1 supports only a 32-bit base address and does not
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* define an inbound window base extended address register.
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*/
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struct pci_inbound_window_regs piw[3];
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__be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
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u8 res21[4];
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__be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
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u8 res22[4];
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__be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
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u8 res23[12];
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__be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
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u8 res24[4];
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__be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
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__be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
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__be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
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__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
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};
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extern int fsl_add_bridge(struct device_node *dev, int is_primary);
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extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
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#endif /* __POWERPC_FSL_PCI_H */
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#endif /* __KERNEL__ */
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