136 lines
4.9 KiB
Plaintext
136 lines
4.9 KiB
Plaintext
* Rockchip AXI PCIe Root Port Bridge DT description
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Required properties:
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- #address-cells: Address representation for root ports, set to <3>
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- #size-cells: Size representation for root ports, set to <2>
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- compatible: Should contain "rockchip,rk3399-pcie"
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- reg: Two register ranges as listed in the reg-names property
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- reg-names: Must include the following names
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- "axi-base"
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- "apb-base"
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "aclk"
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- "aclk-perf"
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- "hclk"
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- "pm"
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- msi-map: Maps a Requester ID to an MSI controller and associated
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msi-specifier data. See ./pci-msi.txt
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- interrupts: Three interrupt entries must be specified.
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- interrupt-names: Must include the following names
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- "sys"
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- "legacy"
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- "client"
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- resets: Must contain seven entries for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following names
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- "core"
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- "mgmt"
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- "mgmt-sticky"
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- "pipe"
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- "pm"
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- "aclk"
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- "pclk"
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- pinctrl-names : The pin control state names
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- pinctrl-0: The "default" pinctrl state
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- interrupt-map-mask and interrupt-map: standard PCI properties
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Required properties for legacy PHY model (deprecated):
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- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
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- phy-names: MUST be "pcie-phy".
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Required properties for per-lane PHY model (preferred):
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- phys: Must contain an phandle to a PHY for each entry in phy-names.
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- phy-names: Must include 4 entries for all 4 lanes even if some of
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them won't be used for your cases. Entries are of the form "pcie-phy-N":
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where N ranges from 0 to 3.
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(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
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for changing the #phy-cells of phy node to support it)
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Optional Property:
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- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
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using 24MHz OSC for RC's PHY.
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- ep-gpios: contain the entry for pre-reset GPIO
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- num-lanes: number of lanes to use
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- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
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- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
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- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
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- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
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*Interrupt controller child node*
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The core controller provides a single interrupt for legacy INTx. The PCIe node
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should contain an interrupt controller node as a target for the PCI
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'interrupt-map' property. This node represents the domain at which the four
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INTx interrupts are decoded and routed.
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Required properties for Interrupt controller child node:
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- interrupt-controller: identifies the node as an interrupt controller
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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Example:
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pcie0: pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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bus-range = <0x0 0x1>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "sys", "legacy", "client";
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assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
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assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
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assigned-clock-rates = <100000000>;
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ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
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ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
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0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
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num-lanes = <4>;
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msi-map = <0x0 &its 0x0 0x1000>;
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reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
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reg-names = "axi-base", "apb-base";
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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/* deprecated legacy PHY model */
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreq>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie0_intc 0>,
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<0 0 0 2 &pcie0_intc 1>,
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<0 0 0 3 &pcie0_intc 2>,
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<0 0 0 4 &pcie0_intc 3>;
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pcie0_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie0: pcie@f8000000 {
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...
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/* preferred per-lane PHY model */
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phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
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phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
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...
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};
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