160 lines
3.9 KiB
C
160 lines
3.9 KiB
C
/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 platform IRQ support
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/irq_cpu.h>
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#include <asm/mach-jz4740/base.h>
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static void __iomem *jz_intc_base;
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#define JZ_REG_INTC_STATUS 0x00
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#define JZ_REG_INTC_MASK 0x04
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#define JZ_REG_INTC_SET_MASK 0x08
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#define JZ_REG_INTC_CLEAR_MASK 0x0c
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#define JZ_REG_INTC_PENDING 0x10
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static irqreturn_t jz4740_cascade(int irq, void *data)
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{
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uint32_t irq_reg;
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irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
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if (irq_reg)
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generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
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return IRQ_HANDLED;
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}
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static void jz4740_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
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{
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struct irq_chip_regs *regs = &gc->chip_types->regs;
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writel(mask, gc->reg_base + regs->enable);
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writel(~mask, gc->reg_base + regs->disable);
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}
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void jz4740_irq_suspend(struct irq_data *data)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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jz4740_irq_set_mask(gc, gc->wake_active);
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}
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void jz4740_irq_resume(struct irq_data *data)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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jz4740_irq_set_mask(gc, gc->mask_cache);
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}
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static struct irqaction jz4740_cascade_action = {
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.handler = jz4740_cascade,
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.name = "JZ4740 cascade interrupt",
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};
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void __init arch_init_irq(void)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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mips_cpu_irq_init();
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jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
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/* Mask all irqs */
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writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
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gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base,
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handle_level_irq);
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gc->wake_enabled = IRQ_MSK(32);
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ct = gc->chip_types;
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ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
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ct->regs.disable = JZ_REG_INTC_SET_MASK;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->chip.irq_suspend = jz4740_irq_suspend;
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ct->chip.irq_resume = jz4740_irq_resume;
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irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
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setup_irq(2, &jz4740_cascade_action);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP2)
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do_IRQ(2);
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else if (pending & STATUSF_IP3)
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do_IRQ(3);
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else
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spurious_interrupt();
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}
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#ifdef CONFIG_DEBUG_FS
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static inline void intc_seq_reg(struct seq_file *s, const char *name,
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unsigned int reg)
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{
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seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
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}
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static int intc_regs_show(struct seq_file *s, void *unused)
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{
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intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
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intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
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intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
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return 0;
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}
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static int intc_regs_open(struct inode *inode, struct file *file)
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{
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return single_open(file, intc_regs_show, NULL);
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}
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static const struct file_operations intc_regs_operations = {
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.open = intc_regs_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int __init intc_debugfs_init(void)
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{
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(void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
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NULL, NULL, &intc_regs_operations);
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return 0;
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}
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subsys_initcall(intc_debugfs_init);
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#endif
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