359 lines
8.8 KiB
C
359 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* simple driver for PWM (Pulse Width Modulator) controller
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*
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* Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
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*
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* Limitations:
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* - When disabled the output is driven to 0 independent of the configured
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* polarity.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#define MX3_PWMCR 0x00 /* PWM Control Register */
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#define MX3_PWMSR 0x04 /* PWM Status Register */
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#define MX3_PWMSAR 0x0C /* PWM Sample Register */
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#define MX3_PWMPR 0x10 /* PWM Period Register */
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#define MX3_PWMCR_FWM GENMASK(27, 26)
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#define MX3_PWMCR_STOPEN BIT(25)
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#define MX3_PWMCR_DOZEN BIT(24)
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#define MX3_PWMCR_WAITEN BIT(23)
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#define MX3_PWMCR_DBGEN BIT(22)
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#define MX3_PWMCR_BCTR BIT(21)
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#define MX3_PWMCR_HCTR BIT(20)
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#define MX3_PWMCR_POUTC GENMASK(19, 18)
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#define MX3_PWMCR_POUTC_NORMAL 0
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#define MX3_PWMCR_POUTC_INVERTED 1
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#define MX3_PWMCR_POUTC_OFF 2
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#define MX3_PWMCR_CLKSRC GENMASK(17, 16)
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#define MX3_PWMCR_CLKSRC_OFF 0
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#define MX3_PWMCR_CLKSRC_IPG 1
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#define MX3_PWMCR_CLKSRC_IPG_HIGH 2
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#define MX3_PWMCR_CLKSRC_IPG_32K 3
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#define MX3_PWMCR_PRESCALER GENMASK(15, 4)
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#define MX3_PWMCR_SWR BIT(3)
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#define MX3_PWMCR_REPEAT GENMASK(2, 1)
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#define MX3_PWMCR_REPEAT_1X 0
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#define MX3_PWMCR_REPEAT_2X 1
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#define MX3_PWMCR_REPEAT_4X 2
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#define MX3_PWMCR_REPEAT_8X 3
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#define MX3_PWMCR_EN BIT(0)
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#define MX3_PWMSR_FWE BIT(6)
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#define MX3_PWMSR_CMP BIT(5)
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#define MX3_PWMSR_ROV BIT(4)
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#define MX3_PWMSR_FE BIT(3)
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#define MX3_PWMSR_FIFOAV GENMASK(2, 0)
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#define MX3_PWMSR_FIFOAV_EMPTY 0
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#define MX3_PWMSR_FIFOAV_1WORD 1
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#define MX3_PWMSR_FIFOAV_2WORDS 2
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#define MX3_PWMSR_FIFOAV_3WORDS 3
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#define MX3_PWMSR_FIFOAV_4WORDS 4
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#define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1)
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#define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \
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(x)) + 1)
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#define MX3_PWM_SWR_LOOP 5
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/* PWMPR register value of 0xffff has the same effect as 0xfffe */
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#define MX3_PWMPR_MAX 0xfffe
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struct pwm_imx27_chip {
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struct clk *clk_ipg;
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struct clk *clk_per;
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void __iomem *mmio_base;
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struct pwm_chip chip;
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/*
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* The driver cannot read the current duty cycle from the hardware if
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* the hardware is disabled. Cache the last programmed duty cycle
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* value to return in that case.
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*/
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unsigned int duty_cycle;
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};
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#define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip, chip)
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static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
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{
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int ret;
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ret = clk_prepare_enable(imx->clk_ipg);
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if (ret)
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return ret;
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ret = clk_prepare_enable(imx->clk_per);
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if (ret) {
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clk_disable_unprepare(imx->clk_ipg);
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return ret;
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}
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return 0;
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}
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static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
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{
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clk_disable_unprepare(imx->clk_per);
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clk_disable_unprepare(imx->clk_ipg);
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}
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static int pwm_imx27_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm, struct pwm_state *state)
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{
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struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
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u32 period, prescaler, pwm_clk, val;
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u64 tmp;
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int ret;
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ret = pwm_imx27_clk_prepare_enable(imx);
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if (ret < 0)
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return ret;
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val = readl(imx->mmio_base + MX3_PWMCR);
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if (val & MX3_PWMCR_EN)
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state->enabled = true;
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else
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state->enabled = false;
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switch (FIELD_GET(MX3_PWMCR_POUTC, val)) {
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case MX3_PWMCR_POUTC_NORMAL:
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state->polarity = PWM_POLARITY_NORMAL;
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break;
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case MX3_PWMCR_POUTC_INVERTED:
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state->polarity = PWM_POLARITY_INVERSED;
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break;
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default:
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dev_warn(chip->dev, "can't set polarity, output disconnected");
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}
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prescaler = MX3_PWMCR_PRESCALER_GET(val);
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pwm_clk = clk_get_rate(imx->clk_per);
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val = readl(imx->mmio_base + MX3_PWMPR);
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period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
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/* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */
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tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler;
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state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk);
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/*
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* PWMSAR can be read only if PWM is enabled. If the PWM is disabled,
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* use the cached value.
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*/
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if (state->enabled)
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val = readl(imx->mmio_base + MX3_PWMSAR);
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else
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val = imx->duty_cycle;
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tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
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state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
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pwm_imx27_clk_disable_unprepare(imx);
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return 0;
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}
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static void pwm_imx27_sw_reset(struct pwm_chip *chip)
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{
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struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
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struct device *dev = chip->dev;
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int wait_count = 0;
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u32 cr;
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writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
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do {
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usleep_range(200, 1000);
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cr = readl(imx->mmio_base + MX3_PWMCR);
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} while ((cr & MX3_PWMCR_SWR) &&
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(wait_count++ < MX3_PWM_SWR_LOOP));
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if (cr & MX3_PWMCR_SWR)
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dev_warn(dev, "software reset timeout\n");
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}
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static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip,
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struct pwm_device *pwm)
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{
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struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
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struct device *dev = chip->dev;
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unsigned int period_ms;
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int fifoav;
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u32 sr;
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sr = readl(imx->mmio_base + MX3_PWMSR);
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fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr);
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if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
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period_ms = DIV_ROUND_UP_ULL(pwm_get_period(pwm),
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NSEC_PER_MSEC);
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msleep(period_ms);
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sr = readl(imx->mmio_base + MX3_PWMSR);
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if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr))
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dev_warn(dev, "there is no free FIFO slot\n");
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}
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}
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static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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unsigned long period_cycles, duty_cycles, prescale;
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struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);
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struct pwm_state cstate;
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unsigned long long c;
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unsigned long long clkrate;
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int ret;
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u32 cr;
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pwm_get_state(pwm, &cstate);
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clkrate = clk_get_rate(imx->clk_per);
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c = clkrate * state->period;
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do_div(c, NSEC_PER_SEC);
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period_cycles = c;
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prescale = period_cycles / 0x10000 + 1;
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period_cycles /= prescale;
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c = clkrate * state->duty_cycle;
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do_div(c, NSEC_PER_SEC);
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duty_cycles = c;
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duty_cycles /= prescale;
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/*
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* according to imx pwm RM, the real period value should be PERIOD
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* value in PWMPR plus 2.
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*/
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if (period_cycles > 2)
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period_cycles -= 2;
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else
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period_cycles = 0;
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/*
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* Wait for a free FIFO slot if the PWM is already enabled, and flush
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* the FIFO if the PWM was disabled and is about to be enabled.
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*/
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if (cstate.enabled) {
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pwm_imx27_wait_fifo_slot(chip, pwm);
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} else {
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ret = pwm_imx27_clk_prepare_enable(imx);
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if (ret)
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return ret;
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pwm_imx27_sw_reset(chip);
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}
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writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
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writel(period_cycles, imx->mmio_base + MX3_PWMPR);
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/*
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* Store the duty cycle for future reference in cases where the
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* MX3_PWMSAR register can't be read (i.e. when the PWM is disabled).
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*/
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imx->duty_cycle = duty_cycles;
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cr = MX3_PWMCR_PRESCALER_SET(prescale) |
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MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN |
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FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) |
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MX3_PWMCR_DBGEN;
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if (state->polarity == PWM_POLARITY_INVERSED)
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cr |= FIELD_PREP(MX3_PWMCR_POUTC,
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MX3_PWMCR_POUTC_INVERTED);
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if (state->enabled)
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cr |= MX3_PWMCR_EN;
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writel(cr, imx->mmio_base + MX3_PWMCR);
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if (!state->enabled)
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pwm_imx27_clk_disable_unprepare(imx);
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return 0;
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}
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static const struct pwm_ops pwm_imx27_ops = {
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.apply = pwm_imx27_apply,
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.get_state = pwm_imx27_get_state,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id pwm_imx27_dt_ids[] = {
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{ .compatible = "fsl,imx27-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
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static int pwm_imx27_probe(struct platform_device *pdev)
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{
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struct pwm_imx27_chip *imx;
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int ret;
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u32 pwmcr;
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imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
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if (imx == NULL)
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return -ENOMEM;
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imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
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if (IS_ERR(imx->clk_ipg))
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return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg),
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"getting ipg clock failed\n");
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imx->clk_per = devm_clk_get(&pdev->dev, "per");
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if (IS_ERR(imx->clk_per))
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return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per),
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"failed to get peripheral clock\n");
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imx->chip.ops = &pwm_imx27_ops;
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imx->chip.dev = &pdev->dev;
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imx->chip.npwm = 1;
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imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(imx->mmio_base))
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return PTR_ERR(imx->mmio_base);
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ret = pwm_imx27_clk_prepare_enable(imx);
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if (ret)
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return ret;
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/* keep clks on if pwm is running */
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pwmcr = readl(imx->mmio_base + MX3_PWMCR);
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if (!(pwmcr & MX3_PWMCR_EN))
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pwm_imx27_clk_disable_unprepare(imx);
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return devm_pwmchip_add(&pdev->dev, &imx->chip);
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}
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static struct platform_driver imx_pwm_driver = {
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.driver = {
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.name = "pwm-imx27",
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.of_match_table = pwm_imx27_dt_ids,
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},
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.probe = pwm_imx27_probe,
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};
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module_platform_driver(imx_pwm_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
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