215 lines
6.4 KiB
C
215 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* drivers/media/i2c/ccs-pll.h
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*
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* Generic MIPI CCS/SMIA/SMIA++ PLL calculator
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*
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* Copyright (C) 2020 Intel Corporation
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* Copyright (C) 2012 Nokia Corporation
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* Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
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*/
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#ifndef CCS_PLL_H
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#define CCS_PLL_H
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#include <linux/bits.h>
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/* CSI-2 or CCP-2 */
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#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00
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#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01
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/* Old SMIA and implementation specific flags */
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/* op pix clock is for all lanes in total normally */
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#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)
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#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
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/* CCS PLL flags */
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#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
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#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3)
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#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
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#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5)
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#define CCS_PLL_FLAG_FIFO_DERATING BIT(6)
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#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7)
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#define CCS_PLL_FLAG_DUAL_PLL BIT(8)
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#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9)
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#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10)
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/**
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* struct ccs_pll_branch_fr - CCS PLL configuration (front)
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*
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* A single branch front-end of the CCS PLL tree.
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*
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* @pre_pll_clk_div: Pre-PLL clock divisor
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* @pll_multiplier: PLL multiplier
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* @pll_ip_clk_freq_hz: PLL input clock frequency
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* @pll_op_clk_freq_hz: PLL output clock frequency
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*/
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struct ccs_pll_branch_fr {
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u16 pre_pll_clk_div;
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u16 pll_multiplier;
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u32 pll_ip_clk_freq_hz;
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u32 pll_op_clk_freq_hz;
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};
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/**
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* struct ccs_pll_branch_bk - CCS PLL configuration (back)
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*
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* A single branch back-end of the CCS PLL tree.
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*
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* @sys_clk_div: System clock divider
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* @pix_clk_div: Pixel clock divider
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* @sys_clk_freq_hz: System clock frequency
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* @pix_clk_freq_hz: Pixel clock frequency
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*/
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struct ccs_pll_branch_bk {
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u16 sys_clk_div;
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u16 pix_clk_div;
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u32 sys_clk_freq_hz;
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u32 pix_clk_freq_hz;
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};
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/**
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* struct ccs_pll - Full CCS PLL configuration
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*
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* All information required to calculate CCS PLL configuration.
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*
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* @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
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* @op_lanes: Number of operational lanes (input)
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* @vt_lanes: Number of video timing lanes (input)
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* @csi2: CSI-2 related parameters
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* @csi2.lanes: The number of the CSI-2 data lanes (input)
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* @binning_vertical: Vertical binning factor (input)
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* @binning_horizontal: Horizontal binning factor (input)
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* @scale_m: Downscaling factor, M component, [16, max] (input)
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* @scale_n: Downscaling factor, N component, typically 16 (input)
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* @bits_per_pixel: Bits per pixel on the output data bus (input)
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* @op_bits_per_lane: Number of bits per OP lane (input)
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* @flags: CCS_PLL_FLAG_* (input)
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* @link_freq: Chosen link frequency (input)
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* @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
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* (input)
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* @vt_fr: Video timing front-end configuration (output)
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* @vt_bk: Video timing back-end configuration (output)
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* @op_fr: Operational timing front-end configuration (output)
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* @op_bk: Operational timing back-end configuration (output)
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* @pixel_rate_csi: Pixel rate on the output data bus (output)
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* @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
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* (output)
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*/
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struct ccs_pll {
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/* input values */
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u8 bus_type;
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u8 op_lanes;
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u8 vt_lanes;
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struct {
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u8 lanes;
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} csi2;
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u8 binning_horizontal;
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u8 binning_vertical;
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u8 scale_m;
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u8 scale_n;
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u8 bits_per_pixel;
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u8 op_bits_per_lane;
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u16 flags;
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u32 link_freq;
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u32 ext_clk_freq_hz;
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/* output values */
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struct ccs_pll_branch_fr vt_fr;
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struct ccs_pll_branch_bk vt_bk;
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struct ccs_pll_branch_fr op_fr;
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struct ccs_pll_branch_bk op_bk;
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u32 pixel_rate_csi;
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u32 pixel_rate_pixel_array;
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};
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/**
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* struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
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*
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* @min_pre_pll_clk_div: Minimum pre-PLL clock divider
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* @max_pre_pll_clk_div: Maximum pre-PLL clock divider
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* @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency
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* @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency
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* @min_pll_multiplier: Minimum PLL multiplier
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* @max_pll_multiplier: Maximum PLL multiplier
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* @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency
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* @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency
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*/
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struct ccs_pll_branch_limits_fr {
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u16 min_pre_pll_clk_div;
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u16 max_pre_pll_clk_div;
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u32 min_pll_ip_clk_freq_hz;
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u32 max_pll_ip_clk_freq_hz;
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u16 min_pll_multiplier;
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u16 max_pll_multiplier;
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u32 min_pll_op_clk_freq_hz;
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u32 max_pll_op_clk_freq_hz;
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};
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/**
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* struct ccs_pll_branch_limits_bk - CCS PLL back-end limits
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*
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* @min_sys_clk_div: Minimum system clock divider
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* @max_sys_clk_div: Maximum system clock divider
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* @min_sys_clk_freq_hz: Minimum system clock frequency
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* @max_sys_clk_freq_hz: Maximum system clock frequency
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* @min_pix_clk_div: Minimum pixel clock divider
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* @max_pix_clk_div: Maximum pixel clock divider
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* @min_pix_clk_freq_hz: Minimum pixel clock frequency
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* @max_pix_clk_freq_hz: Maximum pixel clock frequency
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*/
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struct ccs_pll_branch_limits_bk {
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u16 min_sys_clk_div;
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u16 max_sys_clk_div;
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u32 min_sys_clk_freq_hz;
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u32 max_sys_clk_freq_hz;
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u16 min_pix_clk_div;
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u16 max_pix_clk_div;
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u32 min_pix_clk_freq_hz;
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u32 max_pix_clk_freq_hz;
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};
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/**
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* struct ccs_pll_limits - CCS PLL limits
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*
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* @min_ext_clk_freq_hz: Minimum external clock frequency
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* @max_ext_clk_freq_hz: Maximum external clock frequency
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* @vt_fr: Video timing front-end limits
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* @vt_bk: Video timing back-end limits
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* @op_fr: Operational timing front-end limits
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* @op_bk: Operational timing back-end limits
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* @min_line_length_pck_bin: Minimum line length in pixels, with binning
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* @min_line_length_pck: Minimum line length in pixels without binning
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*/
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struct ccs_pll_limits {
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/* Strict PLL limits */
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u32 min_ext_clk_freq_hz;
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u32 max_ext_clk_freq_hz;
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struct ccs_pll_branch_limits_fr vt_fr;
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struct ccs_pll_branch_limits_bk vt_bk;
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struct ccs_pll_branch_limits_fr op_fr;
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struct ccs_pll_branch_limits_bk op_bk;
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/* Other relevant limits */
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u32 min_line_length_pck_bin;
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u32 min_line_length_pck;
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};
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struct device;
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/**
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* ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters
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*
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* @dev: Device pointer, used for printing messages
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* @limits: Limits specific to the sensor
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* @pll: Given PLL configuration
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*
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* Calculate the CCS PLL configuration based on the limits as well as given
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* device specific, system specific or user configured input data.
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*/
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int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
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struct ccs_pll *pll);
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#endif /* CCS_PLL_H */
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