350 lines
8.9 KiB
C
350 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
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* Copyright 2018, Socionext Inc.
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* Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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*/
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/resource.h>
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/* PHY */
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#define PCL_PHY_CLKCTRL 0x0000
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#define PORT_SEL_MASK GENMASK(11, 9)
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#define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1)
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#define PCL_PHY_TEST_I 0x2000
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#define TESTI_DAT_MASK GENMASK(13, 6)
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#define TESTI_ADR_MASK GENMASK(5, 1)
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#define TESTI_WR_EN BIT(0)
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#define TESTIO_PHY_SHIFT 16
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#define PCL_PHY_TEST_O 0x2004
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#define TESTO_DAT_MASK GENMASK(7, 0)
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#define PCL_PHY_RESET 0x200c
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#define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */
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#define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */
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/* SG */
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#define SG_USBPCIESEL 0x590
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#define SG_USBPCIESEL_PCIE BIT(0)
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/* SC */
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#define SC_US3SRCSEL 0x2244
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#define SC_US3SRCSEL_2LANE GENMASK(9, 8)
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#define PCL_PHY_R00 0
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#define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */
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#define PCL_PHY_R06 6
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#define RX_EQ_ADJ GENMASK(5, 0) /* EQ adjustment value */
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#define RX_EQ_ADJ_VAL 0
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#define PCL_PHY_R26 26
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#define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */
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#define VCO_CTRL_INIT_VAL 5
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#define PCL_PHY_R28 28
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#define VCOPLL_CLMP GENMASK(3, 2) /* Tx VCOPLL clamp mode */
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#define VCOPLL_CLMP_VAL 0
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struct uniphier_pciephy_priv {
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void __iomem *base;
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struct device *dev;
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struct clk *clk, *clk_gio;
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struct reset_control *rst, *rst_gio;
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const struct uniphier_pciephy_soc_data *data;
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};
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struct uniphier_pciephy_soc_data {
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bool is_legacy;
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bool is_dual_phy;
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void (*set_phymode)(struct regmap *regmap);
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};
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static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv,
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int id, u32 data)
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{
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if (id)
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data <<= TESTIO_PHY_SHIFT;
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/* need to read TESTO twice after accessing TESTI */
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writel(data, priv->base + PCL_PHY_TEST_I);
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readl(priv->base + PCL_PHY_TEST_O);
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readl(priv->base + PCL_PHY_TEST_O);
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}
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static u32 uniphier_pciephy_testio_read(struct uniphier_pciephy_priv *priv, int id)
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{
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u32 val = readl(priv->base + PCL_PHY_TEST_O);
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if (id)
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val >>= TESTIO_PHY_SHIFT;
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return val & TESTO_DAT_MASK;
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}
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static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv,
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int id, u32 reg, u32 mask, u32 param)
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{
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u32 val;
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/* read previous data */
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val = FIELD_PREP(TESTI_DAT_MASK, 1);
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val |= FIELD_PREP(TESTI_ADR_MASK, reg);
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uniphier_pciephy_testio_write(priv, id, val);
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val = uniphier_pciephy_testio_read(priv, id);
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/* update value */
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val &= ~mask;
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val |= mask & param;
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val = FIELD_PREP(TESTI_DAT_MASK, val);
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val |= FIELD_PREP(TESTI_ADR_MASK, reg);
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uniphier_pciephy_testio_write(priv, id, val);
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uniphier_pciephy_testio_write(priv, id, val | TESTI_WR_EN);
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uniphier_pciephy_testio_write(priv, id, val);
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/* read current data as dummy */
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val = FIELD_PREP(TESTI_DAT_MASK, 1);
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val |= FIELD_PREP(TESTI_ADR_MASK, reg);
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uniphier_pciephy_testio_write(priv, id, val);
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uniphier_pciephy_testio_read(priv, id);
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}
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static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv)
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{
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u32 val;
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val = readl(priv->base + PCL_PHY_RESET);
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val &= ~PCL_PHY_RESET_N;
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val |= PCL_PHY_RESET_N_MNMODE;
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writel(val, priv->base + PCL_PHY_RESET);
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}
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static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv)
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{
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u32 val;
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val = readl(priv->base + PCL_PHY_RESET);
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val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N;
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writel(val, priv->base + PCL_PHY_RESET);
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}
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static int uniphier_pciephy_init(struct phy *phy)
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{
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struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
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u32 val;
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int ret, id;
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->clk_gio);
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if (ret)
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goto out_clk_disable;
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ret = reset_control_deassert(priv->rst);
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if (ret)
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goto out_clk_gio_disable;
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ret = reset_control_deassert(priv->rst_gio);
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if (ret)
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goto out_rst_assert;
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/* support only 1 port */
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val = readl(priv->base + PCL_PHY_CLKCTRL);
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val &= ~PORT_SEL_MASK;
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val |= PORT_SEL_1;
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writel(val, priv->base + PCL_PHY_CLKCTRL);
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/* legacy controller doesn't have phy_reset and parameters */
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if (priv->data->is_legacy)
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return 0;
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for (id = 0; id < (priv->data->is_dual_phy ? 2 : 1); id++) {
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uniphier_pciephy_set_param(priv, id, PCL_PHY_R00,
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RX_EQ_ADJ_EN, RX_EQ_ADJ_EN);
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uniphier_pciephy_set_param(priv, id, PCL_PHY_R06, RX_EQ_ADJ,
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FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL));
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uniphier_pciephy_set_param(priv, id, PCL_PHY_R26, VCO_CTRL,
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FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL));
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uniphier_pciephy_set_param(priv, id, PCL_PHY_R28, VCOPLL_CLMP,
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FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL));
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}
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usleep_range(1, 10);
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uniphier_pciephy_deassert(priv);
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usleep_range(1, 10);
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return 0;
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out_rst_assert:
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reset_control_assert(priv->rst);
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out_clk_gio_disable:
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clk_disable_unprepare(priv->clk_gio);
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out_clk_disable:
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clk_disable_unprepare(priv->clk);
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return ret;
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}
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static int uniphier_pciephy_exit(struct phy *phy)
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{
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struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
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if (!priv->data->is_legacy)
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uniphier_pciephy_assert(priv);
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reset_control_assert(priv->rst_gio);
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reset_control_assert(priv->rst);
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clk_disable_unprepare(priv->clk_gio);
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clk_disable_unprepare(priv->clk);
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return 0;
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}
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static const struct phy_ops uniphier_pciephy_ops = {
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.init = uniphier_pciephy_init,
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.exit = uniphier_pciephy_exit,
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.owner = THIS_MODULE,
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};
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static int uniphier_pciephy_probe(struct platform_device *pdev)
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{
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struct uniphier_pciephy_priv *priv;
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct regmap *regmap;
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struct phy *phy;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->data = of_device_get_match_data(dev);
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if (WARN_ON(!priv->data))
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return -EINVAL;
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priv->dev = dev;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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if (priv->data->is_legacy) {
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priv->clk_gio = devm_clk_get(dev, "gio");
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if (IS_ERR(priv->clk_gio))
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return PTR_ERR(priv->clk_gio);
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priv->rst_gio =
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devm_reset_control_get_shared(dev, "gio");
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if (IS_ERR(priv->rst_gio))
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return PTR_ERR(priv->rst_gio);
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priv->clk = devm_clk_get(dev, "link");
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if (IS_ERR(priv->clk))
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return PTR_ERR(priv->clk);
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priv->rst = devm_reset_control_get_shared(dev, "link");
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if (IS_ERR(priv->rst))
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return PTR_ERR(priv->rst);
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} else {
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk))
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return PTR_ERR(priv->clk);
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priv->rst = devm_reset_control_get_shared(dev, NULL);
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if (IS_ERR(priv->rst))
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return PTR_ERR(priv->rst);
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}
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phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops);
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if (IS_ERR(phy))
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return PTR_ERR(phy);
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regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
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"socionext,syscon");
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if (!IS_ERR(regmap) && priv->data->set_phymode)
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priv->data->set_phymode(regmap);
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phy_set_drvdata(phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static void uniphier_pciephy_ld20_setmode(struct regmap *regmap)
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{
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regmap_update_bits(regmap, SG_USBPCIESEL,
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SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
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}
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static void uniphier_pciephy_nx1_setmode(struct regmap *regmap)
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{
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regmap_update_bits(regmap, SC_US3SRCSEL,
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SC_US3SRCSEL_2LANE, SC_US3SRCSEL_2LANE);
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}
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static const struct uniphier_pciephy_soc_data uniphier_pro5_data = {
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.is_legacy = true,
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};
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static const struct uniphier_pciephy_soc_data uniphier_ld20_data = {
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.is_legacy = false,
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.is_dual_phy = false,
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.set_phymode = uniphier_pciephy_ld20_setmode,
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};
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static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = {
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.is_legacy = false,
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.is_dual_phy = false,
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};
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static const struct uniphier_pciephy_soc_data uniphier_nx1_data = {
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.is_legacy = false,
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.is_dual_phy = true,
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.set_phymode = uniphier_pciephy_nx1_setmode,
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};
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static const struct of_device_id uniphier_pciephy_match[] = {
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{
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.compatible = "socionext,uniphier-pro5-pcie-phy",
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.data = &uniphier_pro5_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-pcie-phy",
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.data = &uniphier_ld20_data,
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},
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{
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.compatible = "socionext,uniphier-pxs3-pcie-phy",
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.data = &uniphier_pxs3_data,
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},
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{
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.compatible = "socionext,uniphier-nx1-pcie-phy",
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.data = &uniphier_nx1_data,
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, uniphier_pciephy_match);
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static struct platform_driver uniphier_pciephy_driver = {
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.probe = uniphier_pciephy_probe,
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.driver = {
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.name = "uniphier-pcie-phy",
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.of_match_table = uniphier_pciephy_match,
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},
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};
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module_platform_driver(uniphier_pciephy_driver);
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MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
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MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller");
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MODULE_LICENSE("GPL v2");
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