255 lines
6.4 KiB
C
255 lines
6.4 KiB
C
#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/kernel.h>
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#include <asm/segment.h>
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#include <asm/alternative.h>
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#ifdef __KERNEL__
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#define __STR(x) #x
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#define STR(x) __STR(x)
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#define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
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#define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
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/* frame pointer must be last for get_wchan */
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#define SAVE_CONTEXT "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
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#define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
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#define __EXTRA_CLOBBER \
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,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
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/* Save restore flags to clear handle leaking NT */
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#define switch_to(prev,next,last) \
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asm volatile(SAVE_CONTEXT \
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"movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
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"movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
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"call __switch_to\n\t" \
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".globl thread_return\n" \
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"thread_return:\n\t" \
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"movq %%gs:%P[pda_pcurrent],%%rsi\n\t" \
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"movq %P[thread_info](%%rsi),%%r8\n\t" \
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LOCK_PREFIX "btr %[tif_fork],%P[ti_flags](%%r8)\n\t" \
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"movq %%rax,%%rdi\n\t" \
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"jc ret_from_fork\n\t" \
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RESTORE_CONTEXT \
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: "=a" (last) \
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: [next] "S" (next), [prev] "D" (prev), \
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[threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
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[ti_flags] "i" (offsetof(struct thread_info, flags)),\
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[tif_fork] "i" (TIF_FORK), \
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[thread_info] "i" (offsetof(struct task_struct, thread_info)), \
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[pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
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: "memory", "cc" __EXTRA_CLOBBER)
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extern void load_gs_index(unsigned);
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/*
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* Load a segment. Fall back on loading the zero
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* segment if something goes wrong..
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*/
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#define loadsegment(seg,value) \
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asm volatile("\n" \
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"1:\t" \
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"movl %k0,%%" #seg "\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3:\t" \
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"movl %1,%%" #seg "\n\t" \
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"jmp 2b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n\t" \
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".align 8\n\t" \
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".quad 1b,3b\n" \
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".previous" \
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: :"r" (value), "r" (0))
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/*
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* Clear and set 'TS' bit respectively
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*/
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#define clts() __asm__ __volatile__ ("clts")
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static inline unsigned long read_cr0(void)
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{
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unsigned long cr0;
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asm volatile("movq %%cr0,%0" : "=r" (cr0));
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return cr0;
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}
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static inline void write_cr0(unsigned long val)
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{
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asm volatile("movq %0,%%cr0" :: "r" (val));
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}
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static inline unsigned long read_cr3(void)
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{
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unsigned long cr3;
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asm("movq %%cr3,%0" : "=r" (cr3));
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return cr3;
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}
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static inline unsigned long read_cr4(void)
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{
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unsigned long cr4;
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asm("movq %%cr4,%0" : "=r" (cr4));
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return cr4;
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}
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static inline void write_cr4(unsigned long val)
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{
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asm volatile("movq %0,%%cr4" :: "r" (val));
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}
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#define stts() write_cr0(8 | read_cr0())
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#define wbinvd() \
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__asm__ __volatile__ ("wbinvd": : :"memory");
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*/
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static inline void sched_cacheflush(void)
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{
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wbinvd();
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}
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#endif /* __KERNEL__ */
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#define nop() __asm__ __volatile__ ("nop")
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#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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#define __xg(x) ((volatile long *)(x))
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static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
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{
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*ptr = val;
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}
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#define _set_64bit set_64bit
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %k0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 8:
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__asm__ __volatile__("xchgq %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 4:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 8:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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}
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return old;
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}
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#define cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() do {} while(0)
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do {} while(0)
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#endif
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#ifdef CONFIG_UNORDERED_IO
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#define wmb() asm volatile("sfence" ::: "memory")
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#else
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#define wmb() asm volatile("" ::: "memory")
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#endif
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#define read_barrier_depends() do {} while(0)
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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#define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
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#include <linux/irqflags.h>
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void cpu_idle_wait(void);
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extern unsigned long arch_align_stack(unsigned long sp);
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extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
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#endif
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