193 lines
5.0 KiB
C
193 lines
5.0 KiB
C
#ifndef _I386_PGTABLE_3LEVEL_H
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#define _I386_PGTABLE_3LEVEL_H
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/*
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* Intel Physical Address Extension (PAE) Mode - three-level page
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* tables on PPro+ CPUs.
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*
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* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
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*/
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
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#define pud_none(pud) 0
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#define pud_bad(pud) 0
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#define pud_present(pud) 1
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/*
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* Is the pte executable?
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*/
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static inline int pte_x(pte_t pte)
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{
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return !(pte_val(pte) & _PAGE_NX);
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}
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/*
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* All present user-pages with !NX bit are user-executable:
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*/
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static inline int pte_exec(pte_t pte)
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{
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return pte_user(pte) && pte_x(pte);
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}
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/*
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* All present pages with !NX bit are kernel-executable:
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*/
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static inline int pte_exec_kernel(pte_t pte)
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{
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return pte_x(pte);
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}
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#ifndef CONFIG_PARAVIRT
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/* Rules for using set_pte: the pte being assigned *must* be
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* either not present or in a state where the hardware will
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* not attempt to update the pte. In places where this is
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* not possible, use pte_get_and_clear to obtain the old pte
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* value and then use set_pte to update it. -ben
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*/
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static inline void set_pte(pte_t *ptep, pte_t pte)
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{
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ptep->pte_high = pte.pte_high;
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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}
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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/*
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* Since this is only called on user PTEs, and the page fault handler
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* must handle the already racy situation of simultaneous page faults,
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* we are justified in merely clearing the PTE present bit, followed
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* by a set. The ordering here is important.
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*/
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static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
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{
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ptep->pte_low = 0;
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smp_wmb();
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ptep->pte_high = pte.pte_high;
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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}
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#define set_pte_atomic(pteptr,pteval) \
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set_64bit((unsigned long long *)(pteptr),pte_val(pteval))
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#define set_pmd(pmdptr,pmdval) \
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set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
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#define set_pud(pudptr,pudval) \
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(*(pudptr) = (pudval))
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/*
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* For PTEs and PDEs, we must clear the P-bit first when clearing a page table
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* entry, so clear the bottom half first and enforce ordering with a compiler
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* barrier.
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*/
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static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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ptep->pte_low = 0;
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smp_wmb();
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ptep->pte_high = 0;
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}
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static inline void pmd_clear(pmd_t *pmd)
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{
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u32 *tmp = (u32 *)pmd;
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*tmp = 0;
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smp_wmb();
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*(tmp + 1) = 0;
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}
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#endif
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/*
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* Pentium-II erratum A13: in PAE mode we explicitly have to flush
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* the TLB via cr3 if the top-level pgd is changed...
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* We do not let the generic code free and clear pgd entries due to
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* this erratum.
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*/
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static inline void pud_clear (pud_t * pud) { }
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#define pud_page(pud) \
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((struct page *) __va(pud_val(pud) & PAGE_MASK))
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#define pud_page_vaddr(pud) \
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((unsigned long) __va(pud_val(pud) & PAGE_MASK))
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/* Find an entry in the second-level page table.. */
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#define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
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pmd_index(address))
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static inline pte_t raw_ptep_get_and_clear(pte_t *ptep)
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{
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pte_t res;
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/* xchg acts as a barrier before the setting of the high bits */
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res.pte_low = xchg(&ptep->pte_low, 0);
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res.pte_high = ptep->pte_high;
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ptep->pte_high = 0;
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return res;
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}
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#define __HAVE_ARCH_PTE_SAME
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static inline int pte_same(pte_t a, pte_t b)
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{
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return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
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}
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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static inline int pte_none(pte_t pte)
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{
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return !pte.pte_low && !pte.pte_high;
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}
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static inline unsigned long pte_pfn(pte_t pte)
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{
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return (pte.pte_low >> PAGE_SHIFT) |
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(pte.pte_high << (32 - PAGE_SHIFT));
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}
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extern unsigned long long __supported_pte_mask;
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static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
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{
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pte_t pte;
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pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | \
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(pgprot_val(pgprot) >> 32);
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pte.pte_high &= (__supported_pte_mask >> 32);
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pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)) & \
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__supported_pte_mask;
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return pte;
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}
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static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
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{
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return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | \
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pgprot_val(pgprot)) & __supported_pte_mask);
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}
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/*
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* Bits 0, 6 and 7 are taken in the low part of the pte,
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* put the 32 bits of offset into the high part.
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*/
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#define pte_to_pgoff(pte) ((pte).pte_high)
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#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
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#define PTE_FILE_MAX_BITS 32
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/* Encode and de-code a swap entry */
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#define __swp_type(x) (((x).val) & 0x1f)
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#define __swp_offset(x) ((x).val >> 5)
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#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
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#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
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#define __pmd_free_tlb(tlb, x) do { } while (0)
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#define vmalloc_sync_all() ((void)0)
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#endif /* _I386_PGTABLE_3LEVEL_H */
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