477 lines
10 KiB
C
477 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Port on Texas Instruments TMS320C6x architecture
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*
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* Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
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* Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
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*/
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#include <linux/dma-mapping.h>
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#include <linux/memblock.h>
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#include <linux/seq_file.h>
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#include <linux/clkdev.h>
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#include <linux/initrd.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_fdt.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/cache.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/fs.h>
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#include <linux/of.h>
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#include <linux/console.h>
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#include <linux/screen_info.h>
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#include <asm/sections.h>
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#include <asm/div64.h>
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#include <asm/setup.h>
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#include <asm/dscr.h>
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#include <asm/clock.h>
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#include <asm/soc.h>
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#include <asm/special_insns.h>
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static const char *c6x_soc_name;
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struct screen_info screen_info;
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int c6x_num_cores;
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EXPORT_SYMBOL_GPL(c6x_num_cores);
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unsigned int c6x_silicon_rev;
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EXPORT_SYMBOL_GPL(c6x_silicon_rev);
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/*
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* Device status register. This holds information
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* about device configuration needed by some drivers.
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*/
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unsigned int c6x_devstat;
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EXPORT_SYMBOL_GPL(c6x_devstat);
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/*
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* Some SoCs have fuse registers holding a unique MAC
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* address. This is parsed out of the device tree with
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* the resulting MAC being held here.
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*/
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unsigned char c6x_fuse_mac[6];
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unsigned long memory_start;
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unsigned long memory_end;
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EXPORT_SYMBOL(memory_end);
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unsigned long ram_start;
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unsigned long ram_end;
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/* Uncached memory for DMA consistent use (memdma=) */
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static unsigned long dma_start __initdata;
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static unsigned long dma_size __initdata;
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struct cpuinfo_c6x {
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const char *cpu_name;
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const char *cpu_voltage;
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const char *mmu;
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const char *fpu;
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char *cpu_rev;
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unsigned int core_id;
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char __cpu_rev[5];
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};
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static DEFINE_PER_CPU(struct cpuinfo_c6x, cpu_data);
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unsigned int ticks_per_ns_scaled;
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EXPORT_SYMBOL(ticks_per_ns_scaled);
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unsigned int c6x_core_freq;
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static void __init get_cpuinfo(void)
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{
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unsigned cpu_id, rev_id, csr;
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struct clk *coreclk = clk_get_sys(NULL, "core");
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unsigned long core_khz;
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u64 tmp;
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struct cpuinfo_c6x *p;
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struct device_node *node;
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p = &per_cpu(cpu_data, smp_processor_id());
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if (!IS_ERR(coreclk))
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c6x_core_freq = clk_get_rate(coreclk);
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else {
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printk(KERN_WARNING
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"Cannot find core clock frequency. Using 700MHz\n");
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c6x_core_freq = 700000000;
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}
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core_khz = c6x_core_freq / 1000;
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tmp = (uint64_t)core_khz << C6X_NDELAY_SCALE;
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do_div(tmp, 1000000);
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ticks_per_ns_scaled = tmp;
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csr = get_creg(CSR);
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cpu_id = csr >> 24;
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rev_id = (csr >> 16) & 0xff;
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p->mmu = "none";
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p->fpu = "none";
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p->cpu_voltage = "unknown";
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switch (cpu_id) {
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case 0:
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p->cpu_name = "C67x";
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p->fpu = "yes";
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break;
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case 2:
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p->cpu_name = "C62x";
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break;
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case 8:
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p->cpu_name = "C64x";
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break;
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case 12:
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p->cpu_name = "C64x";
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break;
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case 16:
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p->cpu_name = "C64x+";
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p->cpu_voltage = "1.2";
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break;
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case 21:
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p->cpu_name = "C66X";
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p->cpu_voltage = "1.2";
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break;
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default:
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p->cpu_name = "unknown";
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break;
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}
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if (cpu_id < 16) {
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switch (rev_id) {
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case 0x1:
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if (cpu_id > 8) {
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p->cpu_rev = "DM640/DM641/DM642/DM643";
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p->cpu_voltage = "1.2 - 1.4";
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} else {
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p->cpu_rev = "C6201";
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p->cpu_voltage = "2.5";
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}
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break;
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case 0x2:
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p->cpu_rev = "C6201B/C6202/C6211";
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p->cpu_voltage = "1.8";
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break;
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case 0x3:
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p->cpu_rev = "C6202B/C6203/C6204/C6205";
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p->cpu_voltage = "1.5";
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break;
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case 0x201:
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p->cpu_rev = "C6701 revision 0 (early CPU)";
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p->cpu_voltage = "1.8";
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break;
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case 0x202:
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p->cpu_rev = "C6701/C6711/C6712";
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p->cpu_voltage = "1.8";
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break;
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case 0x801:
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p->cpu_rev = "C64x";
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p->cpu_voltage = "1.5";
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break;
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default:
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p->cpu_rev = "unknown";
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}
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} else {
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p->cpu_rev = p->__cpu_rev;
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snprintf(p->__cpu_rev, sizeof(p->__cpu_rev), "0x%x", cpu_id);
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}
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p->core_id = get_coreid();
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for_each_of_cpu_node(node)
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++c6x_num_cores;
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node = of_find_node_by_name(NULL, "soc");
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if (node) {
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if (of_property_read_string(node, "model", &c6x_soc_name))
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c6x_soc_name = "unknown";
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of_node_put(node);
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} else
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c6x_soc_name = "unknown";
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printk(KERN_INFO "CPU%d: %s rev %s, %s volts, %uMHz\n",
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p->core_id, p->cpu_name, p->cpu_rev,
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p->cpu_voltage, c6x_core_freq / 1000000);
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}
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/*
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* Early parsing of the command line
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*/
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static u32 mem_size __initdata;
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/* "mem=" parsing. */
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static int __init early_mem(char *p)
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{
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if (!p)
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return -EINVAL;
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mem_size = memparse(p, &p);
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/* don't remove all of memory when handling "mem={invalid}" */
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if (mem_size == 0)
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return -EINVAL;
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return 0;
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}
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early_param("mem", early_mem);
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/* "memdma=<size>[@<address>]" parsing. */
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static int __init early_memdma(char *p)
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{
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if (!p)
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return -EINVAL;
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dma_size = memparse(p, &p);
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if (*p == '@')
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dma_start = memparse(p, &p);
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return 0;
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}
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early_param("memdma", early_memdma);
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int __init c6x_add_memory(phys_addr_t start, unsigned long size)
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{
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static int ram_found __initdata;
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/* We only handle one bank (the one with PAGE_OFFSET) for now */
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if (ram_found)
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return -EINVAL;
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if (start > PAGE_OFFSET || PAGE_OFFSET >= (start + size))
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return 0;
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ram_start = start;
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ram_end = start + size;
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ram_found = 1;
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return 0;
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}
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/*
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* Do early machine setup and device tree parsing. This is called very
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* early on the boot process.
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*/
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notrace void __init machine_init(unsigned long dt_ptr)
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{
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void *dtb = __va(dt_ptr);
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void *fdt = __dtb_start;
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/* interrupts must be masked */
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set_creg(IER, 2);
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/*
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* Set the Interrupt Service Table (IST) to the beginning of the
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* vector table.
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*/
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set_ist(_vectors_start);
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/*
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* dtb is passed in from bootloader.
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* fdt is linked in blob.
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*/
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if (dtb && dtb != fdt)
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fdt = dtb;
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/* Do some early initialization based on the flat device tree */
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early_init_dt_scan(fdt);
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parse_early_param();
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}
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void __init setup_arch(char **cmdline_p)
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{
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phys_addr_t start, end;
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u64 i;
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printk(KERN_INFO "Initializing kernel\n");
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/* Initialize command line */
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*cmdline_p = boot_command_line;
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memory_end = ram_end;
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memory_end &= ~(PAGE_SIZE - 1);
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if (mem_size && (PAGE_OFFSET + PAGE_ALIGN(mem_size)) < memory_end)
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memory_end = PAGE_OFFSET + PAGE_ALIGN(mem_size);
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/* add block that this kernel can use */
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memblock_add(PAGE_OFFSET, memory_end - PAGE_OFFSET);
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/* reserve kernel text/data/bss */
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memblock_reserve(PAGE_OFFSET,
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PAGE_ALIGN((unsigned long)&_end - PAGE_OFFSET));
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if (dma_size) {
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/* align to cacheability granularity */
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dma_size = CACHE_REGION_END(dma_size);
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if (!dma_start)
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dma_start = memory_end - dma_size;
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/* align to cacheability granularity */
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dma_start = CACHE_REGION_START(dma_start);
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/* reserve DMA memory taken from kernel memory */
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if (memblock_is_region_memory(dma_start, dma_size))
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memblock_reserve(dma_start, dma_size);
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}
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memory_start = PAGE_ALIGN((unsigned int) &_end);
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printk(KERN_INFO "Memory Start=%08lx, Memory End=%08lx\n",
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memory_start, memory_end);
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#ifdef CONFIG_BLK_DEV_INITRD
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/*
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* Reserve initrd memory if in kernel memory.
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*/
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if (initrd_start < initrd_end)
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if (memblock_is_region_memory(initrd_start,
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initrd_end - initrd_start))
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memblock_reserve(initrd_start,
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initrd_end - initrd_start);
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#endif
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init_mm.start_code = (unsigned long) &_stext;
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init_mm.end_code = (unsigned long) &_etext;
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init_mm.end_data = memory_start;
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init_mm.brk = memory_start;
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unflatten_and_copy_device_tree();
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c6x_cache_init();
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/* Set the whole external memory as non-cacheable */
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disable_caching(ram_start, ram_end - 1);
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/* Set caching of external RAM used by Linux */
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for_each_mem_range(i, &start, &end)
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enable_caching(CACHE_REGION_START(start),
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CACHE_REGION_START(end - 1));
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#ifdef CONFIG_BLK_DEV_INITRD
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/*
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* Enable caching for initrd which falls outside kernel memory.
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*/
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if (initrd_start < initrd_end) {
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if (!memblock_is_region_memory(initrd_start,
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initrd_end - initrd_start))
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enable_caching(CACHE_REGION_START(initrd_start),
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CACHE_REGION_START(initrd_end - 1));
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}
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#endif
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/*
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* Disable caching for dma coherent memory taken from kernel memory.
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*/
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if (dma_size && memblock_is_region_memory(dma_start, dma_size))
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disable_caching(dma_start,
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CACHE_REGION_START(dma_start + dma_size - 1));
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/* Initialize the coherent memory allocator */
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coherent_mem_init(dma_start, dma_size);
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max_low_pfn = PFN_DOWN(memory_end);
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min_low_pfn = PFN_UP(memory_start);
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max_pfn = max_low_pfn;
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max_mapnr = max_low_pfn - min_low_pfn;
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/* Get kmalloc into gear */
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paging_init();
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/*
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* Probe for Device State Configuration Registers.
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* We have to do this early in case timer needs to be enabled
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* through DSCR.
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*/
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dscr_probe();
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/* We do this early for timer and core clock frequency */
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c64x_setup_clocks();
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/* Get CPU info */
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get_cpuinfo();
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#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
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conswitchp = &dummy_con;
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#endif
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}
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#define cpu_to_ptr(n) ((void *)((long)(n)+1))
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#define ptr_to_cpu(p) ((long)(p) - 1)
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static int show_cpuinfo(struct seq_file *m, void *v)
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{
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int n = ptr_to_cpu(v);
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struct cpuinfo_c6x *p = &per_cpu(cpu_data, n);
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if (n == 0) {
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seq_printf(m,
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"soc\t\t: %s\n"
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"soc revision\t: 0x%x\n"
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"soc cores\t: %d\n",
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c6x_soc_name, c6x_silicon_rev, c6x_num_cores);
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}
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seq_printf(m,
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"\n"
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"processor\t: %d\n"
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"cpu\t\t: %s\n"
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"core revision\t: %s\n"
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"core voltage\t: %s\n"
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"core id\t\t: %d\n"
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"mmu\t\t: %s\n"
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"fpu\t\t: %s\n"
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"cpu MHz\t\t: %u\n"
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"bogomips\t: %lu.%02lu\n\n",
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n,
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p->cpu_name, p->cpu_rev, p->cpu_voltage,
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p->core_id, p->mmu, p->fpu,
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(c6x_core_freq + 500000) / 1000000,
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(loops_per_jiffy/(500000/HZ)),
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(loops_per_jiffy/(5000/HZ))%100);
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return NULL;
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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const struct seq_operations cpuinfo_op = {
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c_start,
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c_stop,
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c_next,
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show_cpuinfo
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};
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static struct cpu cpu_devices[NR_CPUS];
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static int __init topology_init(void)
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{
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int i;
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for_each_present_cpu(i)
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register_cpu(&cpu_devices[i], i);
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return 0;
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}
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subsys_initcall(topology_init);
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