Clément Léger a38c1e766f riscv: fix misaligned access handling of C.SWSP and C.SDSP ... [ Upstream commit 22e0eb04837a63af111fae35a92f7577676b9bc8 ] This is a backport of a fix that was done in OpenSBI: ec0559eb315b ("lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP"). Unlike C.LWSP/C.LDSP, these encodings can be used with the zero register, so checking that the rs2 field is non-zero is unnecessary. Additionally, the previous check was incorrect since it was checking the immediate field of the instruction instead of the rs2 field. Fixes: 956d705dd2 ("riscv: Unaligned load/store handling for M_MODE") Signed-off-by: Clément Léger <cleger@rivosinc.com> Link: https://lore.kernel.org/r/20231103090223.702340-1-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2023-12-13 18:39:16 +01:00
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include	riscv: mm: Update the comment of CONFIG_PAGE_OFFSET	2023-11-28 17:07:19 +00:00
kernel	riscv: fix misaligned access handling of C.SWSP and C.SDSP	2023-12-13 18:39:16 +01:00
kvm	…
lib	…
mm	riscv: correct pt_level name via pgtable_l5/4_enabled	2023-11-28 17:07:20 +00:00
net	riscv, bpf: Sign-extend return values	2023-10-19 23:08:53 +02:00
purgatory	…
Kbuild	…
Kconfig	…
Kconfig.debug	…
Kconfig.erratas	…
Kconfig.socs	…
Makefile	…