acrn-kernel/Documentation/arm64
Rob Herring 6e3ae2927b arm64: errata: Add Cortex-A520 speculative unprivileged load workaround
commit 471470bc70 upstream.

Implement the workaround for ARM Cortex-A520 erratum 2966298. On an
affected Cortex-A520 core, a speculatively executed unprivileged load
might leak data from a privileged load via a cache side channel. The
issue only exists for loads within a translation regime with the same
translation (e.g. same ASID and VMID). Therefore, the issue only affects
the return to EL0.

The workaround is to execute a TLBI before returning to EL0 after all
loads of privileged data. A non-shareable TLBI to any address is
sufficient.

The workaround isn't necessary if page table isolation (KPTI) is
enabled, but for simplicity it will be. Page table isolation should
normally be disabled for Cortex-A520 as it supports the CSV3 feature
and the E0PD feature (used when KASLR is enabled).

Cc: stable@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230921194156.1050055-2-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-10-10 22:00:39 +02:00
..
acpi_object_usage.rst
amu.rst
arm-acpi.rst
asymmetric-32bit.rst
booting.rst
cpu-feature-registers.rst
elf_hwcaps.rst
features.rst
hugetlbpage.rst
index.rst
kasan-offsets.sh
legacy_instructions.rst
memory-tagging-extension.rst
memory.rst
perf.rst
pointer-authentication.rst
silicon-errata.rst arm64: errata: Add Cortex-A520 speculative unprivileged load workaround 2023-10-10 22:00:39 +02:00
sme.rst
sve.rst
tagged-address-abi.rst
tagged-pointers.rst