286 lines
6.3 KiB
C
286 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/percpu.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <asm/hpet.h>
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#include <asm/time.h>
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#define SMBUS_CFG_BASE (loongson_sysconf.ht_control_base + 0x0300a000)
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#define SMBUS_PCI_REG40 0x40
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#define SMBUS_PCI_REG64 0x64
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#define SMBUS_PCI_REGB4 0xb4
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#define HPET_MIN_CYCLES 16
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#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES * 12)
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static DEFINE_SPINLOCK(hpet_lock);
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DEFINE_PER_CPU(struct clock_event_device, hpet_clockevent_device);
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static unsigned int smbus_read(int offset)
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{
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return *(volatile unsigned int *)(SMBUS_CFG_BASE + offset);
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}
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static void smbus_write(int offset, int data)
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{
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*(volatile unsigned int *)(SMBUS_CFG_BASE + offset) = data;
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}
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static void smbus_enable(int offset, int bit)
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{
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unsigned int cfg = smbus_read(offset);
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cfg |= bit;
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smbus_write(offset, cfg);
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}
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static int hpet_read(int offset)
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{
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return *(volatile unsigned int *)(HPET_MMIO_ADDR + offset);
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}
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static void hpet_write(int offset, int data)
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{
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*(volatile unsigned int *)(HPET_MMIO_ADDR + offset) = data;
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}
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static void hpet_start_counter(void)
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{
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unsigned int cfg = hpet_read(HPET_CFG);
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cfg |= HPET_CFG_ENABLE;
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hpet_write(HPET_CFG, cfg);
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}
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static void hpet_stop_counter(void)
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{
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unsigned int cfg = hpet_read(HPET_CFG);
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cfg &= ~HPET_CFG_ENABLE;
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hpet_write(HPET_CFG, cfg);
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}
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static void hpet_reset_counter(void)
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{
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hpet_write(HPET_COUNTER, 0);
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hpet_write(HPET_COUNTER + 4, 0);
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}
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static void hpet_restart_counter(void)
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{
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hpet_stop_counter();
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hpet_reset_counter();
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hpet_start_counter();
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}
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static void hpet_enable_legacy_int(void)
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{
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/* Do nothing on Loongson-3 */
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}
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static int hpet_set_state_periodic(struct clock_event_device *evt)
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{
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int cfg;
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spin_lock(&hpet_lock);
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pr_info("set clock event to periodic mode!\n");
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/* stop counter */
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hpet_stop_counter();
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/* enables the timer0 to generate a periodic interrupt */
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cfg = hpet_read(HPET_T0_CFG);
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cfg &= ~HPET_TN_LEVEL;
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cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
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HPET_TN_32BIT;
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hpet_write(HPET_T0_CFG, cfg);
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/* set the comparator */
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hpet_write(HPET_T0_CMP, HPET_COMPARE_VAL);
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udelay(1);
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hpet_write(HPET_T0_CMP, HPET_COMPARE_VAL);
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/* start counter */
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hpet_start_counter();
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spin_unlock(&hpet_lock);
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return 0;
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}
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static int hpet_set_state_shutdown(struct clock_event_device *evt)
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{
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int cfg;
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spin_lock(&hpet_lock);
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cfg = hpet_read(HPET_T0_CFG);
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cfg &= ~HPET_TN_ENABLE;
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hpet_write(HPET_T0_CFG, cfg);
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spin_unlock(&hpet_lock);
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return 0;
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}
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static int hpet_set_state_oneshot(struct clock_event_device *evt)
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{
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int cfg;
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spin_lock(&hpet_lock);
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pr_info("set clock event to one shot mode!\n");
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cfg = hpet_read(HPET_T0_CFG);
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/*
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* set timer0 type
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* 1 : periodic interrupt
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* 0 : non-periodic(oneshot) interrupt
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*/
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cfg &= ~HPET_TN_PERIODIC;
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cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
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hpet_write(HPET_T0_CFG, cfg);
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spin_unlock(&hpet_lock);
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return 0;
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}
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static int hpet_tick_resume(struct clock_event_device *evt)
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{
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spin_lock(&hpet_lock);
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hpet_enable_legacy_int();
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spin_unlock(&hpet_lock);
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return 0;
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}
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static int hpet_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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u32 cnt;
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s32 res;
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cnt = hpet_read(HPET_COUNTER);
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cnt += (u32) delta;
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hpet_write(HPET_T0_CMP, cnt);
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res = (s32)(cnt - hpet_read(HPET_COUNTER));
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return res < HPET_MIN_CYCLES ? -ETIME : 0;
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}
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static irqreturn_t hpet_irq_handler(int irq, void *data)
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{
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int is_irq;
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struct clock_event_device *cd;
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unsigned int cpu = smp_processor_id();
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is_irq = hpet_read(HPET_STATUS);
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if (is_irq & HPET_T0_IRS) {
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/* clear the TIMER0 irq status register */
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hpet_write(HPET_STATUS, HPET_T0_IRS);
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cd = &per_cpu(hpet_clockevent_device, cpu);
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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/*
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* hpet address assignation and irq setting should be done in bios.
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* but pmon don't do this, we just setup here directly.
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* The operation under is normal. unfortunately, hpet_setup process
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* is before pci initialize.
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*
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* {
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* struct pci_dev *pdev;
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*
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* pdev = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
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* pci_write_config_word(pdev, SMBUS_PCI_REGB4, HPET_ADDR);
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*
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* ...
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* }
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*/
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static void hpet_setup(void)
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{
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/* set hpet base address */
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smbus_write(SMBUS_PCI_REGB4, HPET_ADDR);
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/* enable decoding of access to HPET MMIO*/
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smbus_enable(SMBUS_PCI_REG40, (1 << 28));
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/* HPET irq enable */
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smbus_enable(SMBUS_PCI_REG64, (1 << 10));
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hpet_enable_legacy_int();
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}
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void __init setup_hpet_timer(void)
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{
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unsigned long flags = IRQF_NOBALANCING | IRQF_TIMER;
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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hpet_setup();
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cd = &per_cpu(hpet_clockevent_device, cpu);
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cd->name = "hpet";
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cd->rating = 100;
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cd->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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cd->set_state_shutdown = hpet_set_state_shutdown;
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cd->set_state_periodic = hpet_set_state_periodic;
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cd->set_state_oneshot = hpet_set_state_oneshot;
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cd->tick_resume = hpet_tick_resume;
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cd->set_next_event = hpet_next_event;
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cd->irq = HPET_T0_IRQ;
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cd->cpumask = cpumask_of(cpu);
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clockevent_set_clock(cd, HPET_FREQ);
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->max_delta_ticks = 0x7fffffff;
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cd->min_delta_ns = clockevent_delta2ns(HPET_MIN_PROG_DELTA, cd);
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cd->min_delta_ticks = HPET_MIN_PROG_DELTA;
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clockevents_register_device(cd);
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if (request_irq(HPET_T0_IRQ, hpet_irq_handler, flags, "hpet", NULL))
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pr_err("Failed to request irq %d (hpet)\n", HPET_T0_IRQ);
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pr_info("hpet clock event device register\n");
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}
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static u64 hpet_read_counter(struct clocksource *cs)
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{
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return (u64)hpet_read(HPET_COUNTER);
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}
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static void hpet_suspend(struct clocksource *cs)
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{
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}
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static void hpet_resume(struct clocksource *cs)
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{
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hpet_setup();
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hpet_restart_counter();
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}
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static struct clocksource csrc_hpet = {
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.name = "hpet",
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/* mips clocksource rating is less than 300, so hpet is better. */
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.rating = 300,
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.read = hpet_read_counter,
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.mask = CLOCKSOURCE_MASK(32),
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/* oneshot mode work normal with this flag */
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.suspend = hpet_suspend,
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.resume = hpet_resume,
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.mult = 0,
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.shift = 10,
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};
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int __init init_hpet_clocksource(void)
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{
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csrc_hpet.mult = clocksource_hz2mult(HPET_FREQ, csrc_hpet.shift);
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return clocksource_register_hz(&csrc_hpet, HPET_FREQ);
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}
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arch_initcall(init_hpet_clocksource);
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