146 lines
3.3 KiB
C
146 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef _UFS_MEDIATEK_H
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#define _UFS_MEDIATEK_H
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#include <linux/bitops.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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/*
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* Vendor specific UFSHCI Registers
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*/
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#define REG_UFS_REFCLK_CTRL 0x144
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#define REG_UFS_EXTREG 0x2100
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#define REG_UFS_MPHYCTRL 0x2200
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#define REG_UFS_MTK_IP_VER 0x2240
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#define REG_UFS_REJECT_MON 0x22AC
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#define REG_UFS_DEBUG_SEL 0x22C0
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#define REG_UFS_PROBE 0x22C8
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#define REG_UFS_DEBUG_SEL_B0 0x22D0
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#define REG_UFS_DEBUG_SEL_B1 0x22D4
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#define REG_UFS_DEBUG_SEL_B2 0x22D8
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#define REG_UFS_DEBUG_SEL_B3 0x22DC
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/*
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* Ref-clk control
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*
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* Values for register REG_UFS_REFCLK_CTRL
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*/
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#define REFCLK_RELEASE 0x0
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#define REFCLK_REQUEST BIT(0)
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#define REFCLK_ACK BIT(1)
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#define REFCLK_REQ_TIMEOUT_US 3000
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#define REFCLK_DEFAULT_WAIT_US 32
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/*
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* Other attributes
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*/
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#define VS_DEBUGCLOCKENABLE 0xD0A1
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#define VS_SAVEPOWERCONTROL 0xD0A6
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#define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
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/*
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* Vendor specific link state
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*/
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enum {
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VS_LINK_DISABLED = 0,
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VS_LINK_DOWN = 1,
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VS_LINK_UP = 2,
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VS_LINK_HIBERN8 = 3,
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VS_LINK_LOST = 4,
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VS_LINK_CFG = 5,
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};
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/*
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* Vendor specific host controller state
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*/
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enum {
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VS_HCE_RESET = 0,
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VS_HCE_BASE = 1,
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VS_HCE_OOCPR_WAIT = 2,
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VS_HCE_DME_RESET = 3,
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VS_HCE_MIDDLE = 4,
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VS_HCE_DME_ENABLE = 5,
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VS_HCE_DEFAULTS = 6,
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VS_HIB_IDLEEN = 7,
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VS_HIB_ENTER = 8,
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VS_HIB_ENTER_CONF = 9,
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VS_HIB_MIDDLE = 10,
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VS_HIB_WAITTIMER = 11,
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VS_HIB_EXIT_CONF = 12,
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VS_HIB_EXIT = 13,
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};
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/*
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* SiP commands
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*/
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#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
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#define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0)
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#define UFS_MTK_SIP_DEVICE_RESET BIT(1)
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#define UFS_MTK_SIP_CRYPTO_CTRL BIT(2)
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#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
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/*
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* VS_DEBUGCLOCKENABLE
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*/
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enum {
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TX_SYMBOL_CLK_REQ_FORCE = 5,
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};
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/*
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* VS_SAVEPOWERCONTROL
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*/
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enum {
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RX_SYMBOL_CLK_GATE_EN = 0,
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SYS_CLK_GATE_EN = 2,
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TX_CLK_GATE_EN = 3,
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};
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/*
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* Host capability
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*/
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enum ufs_mtk_host_caps {
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UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
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UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
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UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
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UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
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};
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struct ufs_mtk_crypt_cfg {
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struct regulator *reg_vcore;
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struct clk *clk_crypt_perf;
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struct clk *clk_crypt_mux;
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struct clk *clk_crypt_lp;
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int vcore_volt;
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};
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struct ufs_mtk_hw_ver {
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u8 step;
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u8 minor;
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u8 major;
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};
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struct ufs_mtk_host {
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struct phy *mphy;
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struct regulator *reg_va09;
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struct reset_control *hci_reset;
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struct reset_control *unipro_reset;
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struct reset_control *crypto_reset;
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struct ufs_hba *hba;
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struct ufs_mtk_crypt_cfg *crypt;
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struct ufs_mtk_hw_ver hw_ver;
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enum ufs_mtk_host_caps caps;
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bool mphy_powered_on;
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bool unipro_lpm;
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bool ref_clk_enabled;
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u16 ref_clk_ungating_wait_us;
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u16 ref_clk_gating_wait_us;
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u32 ip_ver;
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};
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#endif /* !_UFS_MEDIATEK_H */
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