465 lines
10 KiB
C
465 lines
10 KiB
C
/*
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*
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* Programmable Interrupt Controller functions for the Freescale MPC52xx.
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*
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* Copyright (C) 2006 bplan GmbH
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*
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* Based on the code from the 2.4 kernel by
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* Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
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*
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* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 Montavista Software, Inc
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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#undef DEBUG
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/hardirq.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/mpc52xx.h>
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#include "mpc52xx_pic.h"
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/*
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*
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*/
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static struct mpc52xx_intr __iomem *intr;
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static struct mpc52xx_sdma __iomem *sdma;
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static struct irq_host *mpc52xx_irqhost = NULL;
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static unsigned char mpc52xx_map_senses[4] = {
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IRQ_TYPE_LEVEL_HIGH,
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IRQ_TYPE_EDGE_RISING,
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_LEVEL_LOW,
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};
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/*
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*
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*/
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static inline void io_be_setbit(u32 __iomem *addr, int bitno)
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{
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out_be32(addr, in_be32(addr) | (1 << bitno));
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}
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static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
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{
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out_be32(addr, in_be32(addr) & ~(1 << bitno));
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}
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/*
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* IRQ[0-3] interrupt irq_chip
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*/
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static void mpc52xx_extirq_mask(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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io_be_clrbit(&intr->ctrl, 11 - l2irq);
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}
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static void mpc52xx_extirq_unmask(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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io_be_setbit(&intr->ctrl, 11 - l2irq);
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}
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static void mpc52xx_extirq_ack(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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io_be_setbit(&intr->ctrl, 27-l2irq);
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}
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static struct irq_chip mpc52xx_extirq_irqchip = {
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.typename = " MPC52xx IRQ[0-3] ",
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.mask = mpc52xx_extirq_mask,
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.unmask = mpc52xx_extirq_unmask,
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.ack = mpc52xx_extirq_ack,
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};
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/*
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* Main interrupt irq_chip
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*/
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static void mpc52xx_main_mask(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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io_be_setbit(&intr->main_mask, 16 - l2irq);
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}
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static void mpc52xx_main_unmask(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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io_be_clrbit(&intr->main_mask, 16 - l2irq);
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}
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static struct irq_chip mpc52xx_main_irqchip = {
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.typename = "MPC52xx Main",
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.mask = mpc52xx_main_mask,
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.mask_ack = mpc52xx_main_mask,
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.unmask = mpc52xx_main_unmask,
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};
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/*
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* Peripherals interrupt irq_chip
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*/
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static void mpc52xx_periph_mask(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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io_be_setbit(&intr->per_mask, 31 - l2irq);
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}
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static void mpc52xx_periph_unmask(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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io_be_clrbit(&intr->per_mask, 31 - l2irq);
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}
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static struct irq_chip mpc52xx_periph_irqchip = {
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.typename = "MPC52xx Peripherals",
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.mask = mpc52xx_periph_mask,
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.mask_ack = mpc52xx_periph_mask,
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.unmask = mpc52xx_periph_unmask,
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};
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/*
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* SDMA interrupt irq_chip
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*/
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static void mpc52xx_sdma_mask(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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io_be_setbit(&sdma->IntMask, l2irq);
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}
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static void mpc52xx_sdma_unmask(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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io_be_clrbit(&sdma->IntMask, l2irq);
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}
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static void mpc52xx_sdma_ack(unsigned int virq)
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{
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int irq;
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int l2irq;
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irq = irq_map[virq].hwirq;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
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out_be32(&sdma->IntPend, 1 << l2irq);
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}
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static struct irq_chip mpc52xx_sdma_irqchip = {
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.typename = "MPC52xx SDMA",
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.mask = mpc52xx_sdma_mask,
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.unmask = mpc52xx_sdma_unmask,
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.ack = mpc52xx_sdma_ack,
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};
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/*
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* irq_host
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*/
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static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
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u32 * intspec, unsigned int intsize,
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irq_hw_number_t * out_hwirq,
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unsigned int *out_flags)
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{
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int intrvect_l1;
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int intrvect_l2;
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int intrvect_type;
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int intrvect_linux;
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if (intsize != 3)
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return -1;
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intrvect_l1 = (int)intspec[0];
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intrvect_l2 = (int)intspec[1];
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intrvect_type = (int)intspec[2];
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intrvect_linux =
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(intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
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intrvect_linux |=
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(intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
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pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
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intrvect_l2);
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*out_hwirq = intrvect_linux;
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*out_flags = mpc52xx_map_senses[intrvect_type];
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return 0;
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}
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/*
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* this function retrieves the correct IRQ type out
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* of the MPC regs
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* Only externals IRQs needs this
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*/
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static int mpc52xx_irqx_gettype(int irq)
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{
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int type;
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u32 ctrl_reg;
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ctrl_reg = in_be32(&intr->ctrl);
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type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
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return mpc52xx_map_senses[type];
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}
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static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t irq)
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{
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int l1irq;
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int l2irq;
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struct irq_chip *good_irqchip;
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void *good_handle;
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int type;
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l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
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l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
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/*
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* Most of ours IRQs will be level low
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* Only external IRQs on some platform may be others
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*/
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type = IRQ_TYPE_LEVEL_LOW;
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switch (l1irq) {
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case MPC52xx_IRQ_L1_CRIT:
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pr_debug("%s: Critical. l2=%x\n", __func__, l2irq);
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BUG_ON(l2irq != 0);
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type = mpc52xx_irqx_gettype(l2irq);
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good_irqchip = &mpc52xx_extirq_irqchip;
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break;
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case MPC52xx_IRQ_L1_MAIN:
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pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
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if ((l2irq >= 1) && (l2irq <= 3)) {
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type = mpc52xx_irqx_gettype(l2irq);
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good_irqchip = &mpc52xx_extirq_irqchip;
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} else {
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good_irqchip = &mpc52xx_main_irqchip;
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}
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break;
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case MPC52xx_IRQ_L1_PERP:
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pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
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good_irqchip = &mpc52xx_periph_irqchip;
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break;
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case MPC52xx_IRQ_L1_SDMA:
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pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
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good_irqchip = &mpc52xx_sdma_irqchip;
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break;
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default:
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pr_debug("%s: Error, unknown L1 IRQ (0x%x)\n", __func__, l1irq);
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printk(KERN_ERR "Unknow IRQ!\n");
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return -EINVAL;
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}
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switch (type) {
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_EDGE_RISING:
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good_handle = handle_edge_irq;
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break;
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default:
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good_handle = handle_level_irq;
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}
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set_irq_chip_and_handler(virq, good_irqchip, good_handle);
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pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
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(int)irq, type);
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return 0;
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}
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static struct irq_host_ops mpc52xx_irqhost_ops = {
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.xlate = mpc52xx_irqhost_xlate,
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.map = mpc52xx_irqhost_map,
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};
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/*
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* init (public)
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*/
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void __init mpc52xx_init_irq(void)
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{
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u32 intr_ctrl;
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struct device_node *picnode;
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/* Remap the necessary zones */
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picnode = of_find_compatible_node(NULL, NULL, "mpc5200-pic");
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intr = mpc52xx_find_and_map("mpc5200-pic");
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if (!intr)
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panic(__FILE__ ": find_and_map failed on 'mpc5200-pic'. "
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"Check node !");
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sdma = mpc52xx_find_and_map("mpc5200-bestcomm");
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if (!sdma)
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panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. "
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"Check node !");
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/* Disable all interrupt sources. */
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out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
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out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
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out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
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out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
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intr_ctrl = in_be32(&intr->ctrl);
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intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
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intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
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0x00001000 | /* MEE master external enable */
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0x00000000 | /* 0 means disable IRQ 0-3 */
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0x00000001; /* CEb route critical normally */
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out_be32(&intr->ctrl, intr_ctrl);
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/* Zero a bunch of the priority settings. */
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out_be32(&intr->per_pri1, 0);
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out_be32(&intr->per_pri2, 0);
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out_be32(&intr->per_pri3, 0);
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out_be32(&intr->main_pri1, 0);
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out_be32(&intr->main_pri2, 0);
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/*
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* As last step, add an irq host to translate the real
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* hw irq information provided by the ofw to linux virq
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*/
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mpc52xx_irqhost = irq_alloc_host(picnode, IRQ_HOST_MAP_LINEAR,
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MPC52xx_IRQ_HIGHTESTHWIRQ,
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&mpc52xx_irqhost_ops, -1);
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if (!mpc52xx_irqhost)
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panic(__FILE__ ": Cannot allocate the IRQ host\n");
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printk(KERN_INFO "MPC52xx PIC is up and running!\n");
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}
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/*
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* get_irq (public)
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*/
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unsigned int mpc52xx_get_irq(void)
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{
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u32 status;
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int irq = NO_IRQ_IGNORE;
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status = in_be32(&intr->enc_status);
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if (status & 0x00000400) { /* critical */
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irq = (status >> 8) & 0x3;
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if (irq == 2) /* high priority peripheral */
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goto peripheral;
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irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
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MPC52xx_IRQ_L1_MASK;
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} else if (status & 0x00200000) { /* main */
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irq = (status >> 16) & 0x1f;
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if (irq == 4) /* low priority peripheral */
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goto peripheral;
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irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
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MPC52xx_IRQ_L1_MASK;
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} else if (status & 0x20000000) { /* peripheral */
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peripheral:
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irq = (status >> 24) & 0x1f;
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if (irq == 0) { /* bestcomm */
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status = in_be32(&sdma->IntPend);
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irq = ffs(status) - 1;
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irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
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MPC52xx_IRQ_L1_MASK;
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} else {
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irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
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MPC52xx_IRQ_L1_MASK;
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}
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}
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pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
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irq_linear_revmap(mpc52xx_irqhost, irq));
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return irq_linear_revmap(mpc52xx_irqhost, irq);
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}
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