169 lines
4.5 KiB
C
169 lines
4.5 KiB
C
#include <linux/compiler.h>
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#include <linux/mm.h>
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#include <linux/signal.h>
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#include <linux/smp.h>
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#include <asm/asm.h>
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#include <asm/bootinfo.h>
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#include <asm/byteorder.h>
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#include <asm/cpu.h>
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#include <asm/inst.h>
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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#include <asm/branch.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/cacheflush.h>
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#include <asm/fpu_emulator.h>
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#include "ieee754.h"
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#include "dsemul.h"
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/* Strap kernel emulator for full MIPS IV emulation */
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#ifdef __mips
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#undef __mips
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#endif
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#define __mips 4
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/*
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* Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when
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* we have to emulate the instruction in a COP1 branch delay slot. Do
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* not change cp0_epc due to the instruction
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*
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* According to the spec:
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* 1) it shouldnt be a branch :-)
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* 2) it can be a COP instruction :-(
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* 3) if we are tring to run a protected memory space we must take
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* special care on memory access instructions :-(
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*/
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/*
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* "Trampoline" return routine to catch exception following
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* execution of delay-slot instruction execution.
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*/
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struct emuframe {
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mips_instruction emul;
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mips_instruction badinst;
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mips_instruction cookie;
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unsigned long epc;
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};
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int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
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{
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extern asmlinkage void handle_dsemulret(void);
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mips_instruction *dsemul_insns;
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struct emuframe *fr;
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int err;
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if (ir == 0) { /* a nop is easy */
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regs->cp0_epc = cpc;
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regs->cp0_cause &= ~CAUSEF_BD;
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return 0;
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}
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#ifdef DSEMUL_TRACE
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printk("dsemul %lx %lx\n", regs->cp0_epc, cpc);
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#endif
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/*
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* The strategy is to push the instruction onto the user stack
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* and put a trap after it which we can catch and jump to
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* the required address any alternative apart from full
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* instruction emulation!!.
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*
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* Algorithmics used a system call instruction, and
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* borrowed that vector. MIPS/Linux version is a bit
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* more heavyweight in the interests of portability and
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* multiprocessor support. For Linux we generate a
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* an unaligned access and force an address error exception.
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*
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* For embedded systems (stand-alone) we prefer to use a
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* non-existing CP1 instruction. This prevents us from emulating
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* branches, but gives us a cleaner interface to the exception
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* handler (single entry point).
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*/
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/* Ensure that the two instructions are in the same cache line */
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dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
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fr = (struct emuframe *) dsemul_insns;
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/* Verify that the stack pointer is not competely insane */
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if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
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return SIGBUS;
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err = __put_user(ir, &fr->emul);
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err |= __put_user((mips_instruction)BADINST, &fr->badinst);
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err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
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err |= __put_user(cpc, &fr->epc);
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if (unlikely(err)) {
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fpuemustats.errors++;
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return SIGBUS;
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}
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regs->cp0_epc = (unsigned long) &fr->emul;
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flush_cache_sigtramp((unsigned long)&fr->badinst);
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return SIGILL; /* force out of emulation loop */
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}
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int do_dsemulret(struct pt_regs *xcp)
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{
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struct emuframe *fr;
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unsigned long epc;
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u32 insn, cookie;
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int err = 0;
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fr = (struct emuframe *) (xcp->cp0_epc - sizeof(mips_instruction));
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/*
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* If we can't even access the area, something is very wrong, but we'll
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* leave that to the default handling
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*/
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if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe)))
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return 0;
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/*
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* Do some sanity checking on the stackframe:
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*
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* - Is the instruction pointed to by the EPC an BADINST?
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* - Is the following memory word the BD_COOKIE?
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*/
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err = __get_user(insn, &fr->badinst);
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err |= __get_user(cookie, &fr->cookie);
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if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) {
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fpuemustats.errors++;
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return 0;
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}
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/*
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* At this point, we are satisfied that it's a BD emulation trap. Yes,
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* a user might have deliberately put two malformed and useless
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* instructions in a row in his program, in which case he's in for a
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* nasty surprise - the next instruction will be treated as a
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* continuation address! Alas, this seems to be the only way that we
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* can handle signals, recursion, and longjmps() in the context of
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* emulating the branch delay instruction.
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*/
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#ifdef DSEMUL_TRACE
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printk("dsemulret\n");
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#endif
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if (__get_user(epc, &fr->epc)) { /* Saved EPC */
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/* This is not a good situation to be in */
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force_sig(SIGBUS, current);
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return 0;
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}
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/* Set EPC to return to post-branch instruction */
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xcp->cp0_epc = epc;
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return 1;
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}
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