acrn-kernel/arch/x86/events/intel
Paolo Bonzini 493d556278 KVM: x86/pmu: fix masking logic for MSR_CORE_PERF_GLOBAL_CTRL
commit 971079464001c6856186ca137778e534d983174a upstream.

When commit c59a1f106f ("KVM: x86/pmu: Add IA32_PEBS_ENABLE
MSR emulation for extended PEBS") switched the initialization of
cpuc->guest_switch_msrs to use compound literals, it screwed up
the boolean logic:

+	u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
...
-	arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
-	arr[0].guest &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
+               .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask),

Before the patch, the value of arr[0].guest would have been intel_ctrl &
~cpuc->intel_ctrl_host_mask & ~pebs_mask.  The intent is to always treat
PEBS events as host-only because, while the guest runs, there is no way
to tell the processor about the virtual address where to put PEBS records
intended for the host.

Unfortunately, the new expression can be expanded to

	(intel_ctrl & ~cpuc->intel_ctrl_host_mask) | (intel_ctrl & ~pebs_mask)

which makes no sense; it includes any bit that isn't *both* marked as
exclude_guest and using PEBS.  So, reinstate the old logic.  Another
way to write it could be "intel_ctrl & ~(cpuc->intel_ctrl_host_mask |
pebs_mask)", presumably the intention of the author of the faulty.
However, I personally find the repeated application of A AND NOT B to
be a bit more readable.

This shows up as guest failures when running concurrent long-running
perf workloads on the host, and was reported to happen with rcutorture.
All guests on a given host would die simultaneously with something like an
instruction fault or a segmentation violation.

Reported-by: Paul E. McKenney <paulmck@kernel.org>
Analyzed-by: Sean Christopherson <seanjc@google.com>
Tested-by: Paul E. McKenney <paulmck@kernel.org>
Cc: stable@vger.kernel.org
Fixes: c59a1f106f ("KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS")
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-01-10 17:10:21 +01:00
..
Makefile perf/x86/intel/uncore: Parse uncore discovery tables 2021-04-02 10:04:54 +02:00
bts.c perf/x86: Add compiler barrier after updating BTS 2021-09-17 15:08:38 +02:00
core.c KVM: x86/pmu: fix masking logic for MSR_CORE_PERF_GLOBAL_CTRL 2024-01-10 17:10:21 +01:00
cstate.c perf/x86/intel/cstate: Add Emerald Rapids 2023-02-09 11:28:12 +01:00
ds.c perf/x86/intel/ds: Fix the conversion from TSC to perf time 2023-03-10 09:32:45 +01:00
knc.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
lbr.c perf/x86/core: Zero @lbr instead of returning -1 in x86_perf_get_lbr() stub 2023-05-17 11:53:27 +02:00
p4.c perf/x86/p4: Remove perfctr_second_write quirk 2022-09-07 21:54:04 +02:00
p6.c x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping 2018-02-15 01:15:52 +01:00
pt.c perf/x86/intel/pt: Fix sampling using single range output 2022-11-16 10:12:59 +01:00
pt.h perf/x86/intel/pt: Prevent redundant WRMSRs 2019-11-13 11:06:18 +01:00
uncore.c perf/x86/intel/uncore: Add Meteor Lake support 2023-03-10 09:33:47 +01:00
uncore.h perf/x86/intel/uncore: Add Meteor Lake support 2023-03-10 09:33:47 +01:00
uncore_discovery.c perf/x86/uncore: Don't WARN_ON_ONCE() for a broken discovery table 2023-12-20 17:00:13 +01:00
uncore_discovery.h perf/x86/intel/uncore: Make uncore_discovery clean for 64 bit addresses 2022-03-01 16:19:01 +01:00
uncore_nhmex.c perf/x86/intel/uncore: Correct fixed counter index check for NHM 2018-05-31 12:36:28 +02:00
uncore_snb.c perf/x86/intel/uncore: Add Meteor Lake support 2023-03-10 09:33:47 +01:00
uncore_snbep.c perf/x86/uncore: Correct the number of CHAs on EMR 2023-09-13 09:43:04 +02:00