261 lines
7.4 KiB
YAML
261 lines
7.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR MIT)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/mscc,ocelot.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Ocelot Switch Family Device Tree Bindings
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maintainers:
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- Vladimir Oltean <vladimir.oltean@nxp.com>
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- Claudiu Manoil <claudiu.manoil@nxp.com>
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- Alexandre Belloni <alexandre.belloni@bootlin.com>
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- UNGLinuxDriver@microchip.com
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description: |
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There are multiple switches which are either part of the Ocelot-1 family, or
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derivatives of this architecture. These switches can be found embedded in
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various SoCs and accessed using MMIO, or as discrete chips and accessed over
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SPI or PCIe. The present DSA binding shall be used when the host controlling
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them performs packet I/O primarily through an Ethernet port of the switch
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(which is attached to an Ethernet port of the host), rather than through
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Frame DMA or register-based I/O.
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VSC9953 (Seville):
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This is found in the NXP T1040, where it is a memory-mapped platform
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device.
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The following PHY interface types are supported:
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- phy-mode = "internal": on ports 8 and 9
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- phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
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- phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
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- phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7
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VSC9959 (Felix):
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This is found in the NXP LS1028A. It is a PCI device, part of the larger
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enetc root complex. As a result, the ethernet-switch node is a sub-node of
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the PCIe root complex node and its "reg" property conforms to the parent
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node bindings, describing it as PF 5 of device 0, bus 0.
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If any external switch port is enabled, the enetc PF2 (enetc_port2) should
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be enabled as well. This is because the internal MDIO bus (exposed through
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EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc
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port 2 and not to Felix.
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The following PHY interface types are supported:
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- phy-mode = "internal": on ports 4 and 5
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- phy-mode = "sgmii": on ports 0, 1, 2, 3
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- phy-mode = "qsgmii": on ports 0, 1, 2, 3
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- phy-mode = "usxgmii": on ports 0, 1, 2, 3
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- phy-mode = "1000base-x": on ports 0, 1, 2, 3
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- phy-mode = "2500base-x": on ports 0, 1, 2, 3
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properties:
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compatible:
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enum:
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- mscc,vsc9953-switch
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- pci1957,eef0
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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description:
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Used to signal availability of PTP TX timestamps, and state changes of
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the MAC merge layer of ports that support Frame Preemption.
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little-endian: true
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big-endian: true
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required:
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- compatible
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- reg
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allOf:
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- $ref: dsa.yaml#
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- if:
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properties:
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compatible:
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const: pci1957,eef0
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then:
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required:
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- interrupts
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unevaluatedProperties: false
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examples:
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# Felix VSC9959 (NXP LS1028A)
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie { /* Integrated Endpoint Root Complex */
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#address-cells = <3>;
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#size-cells = <2>;
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ethernet-switch@0,5 {
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compatible = "pci1957,eef0";
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reg = <0x000500 0 0 0 0>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phy-mode = "qsgmii";
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phy-handle = <&phy0>;
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managed = "in-band-status";
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};
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port@1 {
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reg = <1>;
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phy-mode = "qsgmii";
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phy-handle = <&phy1>;
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managed = "in-band-status";
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};
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port@2 {
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reg = <2>;
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phy-mode = "qsgmii";
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phy-handle = <&phy2>;
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managed = "in-band-status";
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};
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port@3 {
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reg = <3>;
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phy-mode = "qsgmii";
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phy-handle = <&phy3>;
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managed = "in-band-status";
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};
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port@4 {
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reg = <4>;
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ethernet = <&enetc_port2>;
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phy-mode = "internal";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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port@5 {
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reg = <5>;
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ethernet = <&enetc_port3>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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# Seville VSC9953 (NXP T1040)
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- |
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ethernet-switch@800000 {
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compatible = "mscc,vsc9953-switch";
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reg = <0x800000 0x290000>;
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little-endian;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phy-mode = "qsgmii";
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phy-handle = <&phy0>;
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managed = "in-band-status";
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};
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port@1 {
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reg = <1>;
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phy-mode = "qsgmii";
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phy-handle = <&phy1>;
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managed = "in-band-status";
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};
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port@2 {
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reg = <2>;
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phy-mode = "qsgmii";
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phy-handle = <&phy2>;
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managed = "in-band-status";
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};
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port@3 {
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reg = <3>;
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phy-mode = "qsgmii";
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phy-handle = <&phy3>;
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managed = "in-band-status";
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};
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port@4 {
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reg = <4>;
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phy-mode = "qsgmii";
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phy-handle = <&phy4>;
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managed = "in-band-status";
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};
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port@5 {
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reg = <5>;
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phy-mode = "qsgmii";
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phy-handle = <&phy5>;
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managed = "in-band-status";
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};
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port@6 {
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reg = <6>;
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phy-mode = "qsgmii";
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phy-handle = <&phy6>;
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managed = "in-band-status";
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};
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port@7 {
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reg = <7>;
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phy-mode = "qsgmii";
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phy-handle = <&phy7>;
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managed = "in-band-status";
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};
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port@8 {
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reg = <8>;
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phy-mode = "internal";
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ethernet = <&enet0>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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port@9 {
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reg = <9>;
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phy-mode = "internal";
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ethernet = <&enet1>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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