Commit Graph

9 Commits

Author SHA1 Message Date
Zheng Zengkai 5860800e86 Documentation/features: Update the arch support status files
The arch support status files don't match reality as of v5.19-rc1,
use the features-refresh.sh to refresh all the arch-support.txt files
in place.  The main effect is to add entries for the new loong
architecture.

Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
Link: https://lore.kernel.org/r/20220609025656.143460-1-zhengzengkai@huawei.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2022-06-09 09:35:57 -06:00
Arnd Bergmann fba2689ee7 Merge branch 'remove-h8300' of git://git.infradead.org/users/hch/misc into asm-generic
* 'remove-h8300' of git://git.infradead.org/users/hch/misc:
  remove the h8300 architecture

This is clearly the least actively maintained architecture we have at
the moment, and probably the least useful. It is now the only one that
does not support MMUs at all, and most of the boards only support 4MB
of RAM, out of which the defconfig kernel needs more than half just
for .text/.data.

Guenter Roeck did the original patch to remove the architecture in 2013
after it had already been obsolete for a while, and Yoshinori Sato brought
it back in a much more modern form in 2015. Looking at the git history
since the reinstantiation, it's clear that almost all commits in the tree
are build fixes or cross-architecture cleanups:

$ git log --no-merges --format=%an v4.5.. arch/h8300/  | sort | uniq
-c | sort -rn | head -n 12
     25 Masahiro Yamada
     18 Christoph Hellwig
     14 Mike Rapoport
      9 Arnd Bergmann
      8 Mark Rutland
      7 Peter Zijlstra
      6 Kees Cook
      6 Ingo Molnar
      6 Al Viro
      5 Randy Dunlap
      4 Yury Norov

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-04 14:42:49 +02:00
Alan Kao aec499c75c nds32: Remove the architecture
The nds32 architecture, also known as AndeStar V3, is a custom 32-bit
RISC target designed by Andes Technologies. Support was added to the
kernel in 2016 as the replacement RISC-V based V5 processors were
already announced, and maintained by (current or former) Andes
employees.

As explained by Alan Kao, new customers are now all using RISC-V,
and all known nds32 users are already on longterm stable kernels
provided by Andes, with no development work going into mainline
support any more.

While the port is still in a reasonably good shape, it only gets
worse over time without active maintainers, so it seems best
to remove it before it becomes unusable. As always, if it turns
out that there are mainline users after all, and they volunteer
to maintain the port in the future, the removal can be reverted.

Link: https://lore.kernel.org/linux-mm/YhdWNLUhk+x9RAzU@yamatobi.andestech.com/
Link: https://lore.kernel.org/lkml/20220302065213.82702-1-alankao@andestech.com/
Link: https://www.andestech.com/en/products-solutions/andestar-architecture/
Signed-off-by: Alan Kao <alankao@andestech.com>
[arnd: rewrite changelog to provide more background]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-07 13:54:59 +01:00
Christoph Hellwig 1c4b5ecb7e remove the h8300 architecture
Signed-off-by: Christoph Hellwig <hch@lst.de>
2022-02-23 08:52:50 +01:00
Arnd Bergmann a910f43efd Documentation: features: refresh feature list
Run the update script to document the recent feature additions
on riscv, mips and csky.

Fixes: c109f42450 ("csky: Add kmemleak support")
Fixes: 8b3165e545 ("MIPS: Enable GCOV")
Fixes: 1ddc96bd42 ("MIPS: kernel: Support extracting off-line stack traces from user-space with perf")
Fixes: 74784081aa ("riscv: Add uprobes supported")
Fixes: 829adda597 ("riscv: Add KPROBES_ON_FTRACE supported")
Fixes: c22b0bcb1d ("riscv: Add kprobes supported")
Fixes: dcdc7a53a8 ("RISC-V: Implement ptrace regs and stack API")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210225142841.3385428-2-arnd@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2021-02-25 11:25:57 -07:00
Arnd Bergmann 4f3c8320c7 Documentation: features: remove c6x references
The references to arch/c6x are obsolete now that the architecture
is gone. Remove them.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210225142841.3385428-1-arnd@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2021-02-25 11:25:57 -07:00
Tobias Klauser f30c3ff3f0 Documentation/features: refresh RISC-V arch support files
Support for these was added by the following commits:

  f2c9699f65 ("riscv: Add STACKPROTECTOR supported")
  3c46979829 ("riscv: Enable LOCKDEP_SUPPORT & fixup TRACE_IRQFLAGS_SUPPORT").
  ed48b297fe ("riscv: Enable context tracking")
  cbb3d91d3b ("riscv: Add kmemleak support")

Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Link: https://lore.kernel.org/r/20200810095000.32092-1-tklauser@distanz.ch
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2020-08-11 10:39:21 -06:00
Tobias Klauser db6f369d5b Documentation/features: Remove unicore32 from kcov and kmemleak
Commit 3839a74607 ("Documentation/features: Add kcov") and
commit 4641961cff ("Documentation/features: Add kmemleak") were added
shortly after the unicore32 port was removed in commit fb37409a01
("arch: remove unicore32 port"). Remove the unicore32 feature lines from
kcov and kmemleak as well.

Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Link: https://lore.kernel.org/r/20200707090922.4746-1-tklauser@distanz.ch
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2020-07-13 09:57:50 -06:00
Tobias Klauser 4641961cff Documentation/features: Add kmemleak
Replace the manually curated list for supported archs in
Documentation/dev-tools/kmemleak.rst by a Documentation/features entry.

Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Link: https://lore.kernel.org/r/20200627091510.28210-1-tklauser@distanz.ch
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
2020-07-05 14:14:02 -06:00