clk: samsung: remove s3c24xx specific pll bits
With the s3c24xx clk driver gone, the portions of the pll driver for it can also be removed. Suggested-by: Chanwoo Choi <cwchoi00@gmail.com> Link: https://lore.kernel.org/linux-arm-kernel/0e0eff12-d8ea-72e9-d135-4259dda9a750@gmail.com/ Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
594b3caeaf
commit
fa0d876fa1
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@ -940,169 +940,6 @@ static const struct clk_ops samsung_pll6553_clk_ops = {
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.recalc_rate = samsung_pll6553_recalc_rate,
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};
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/*
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* PLL Clock Type of S3C24XX before S3C2443
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*/
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#define PLLS3C2410_MDIV_MASK (0xff)
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#define PLLS3C2410_PDIV_MASK (0x1f)
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#define PLLS3C2410_SDIV_MASK (0x3)
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#define PLLS3C2410_MDIV_SHIFT (12)
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#define PLLS3C2410_PDIV_SHIFT (4)
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#define PLLS3C2410_SDIV_SHIFT (0)
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#define PLLS3C2410_ENABLE_REG_OFFSET 0x10
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static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct samsung_clk_pll *pll = to_clk_pll(hw);
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u32 pll_con, mdiv, pdiv, sdiv;
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u64 fvco = parent_rate;
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pll_con = readl_relaxed(pll->con_reg);
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mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
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pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
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sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
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fvco *= (mdiv + 8);
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do_div(fvco, (pdiv + 2) << sdiv);
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return (unsigned int)fvco;
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}
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static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct samsung_clk_pll *pll = to_clk_pll(hw);
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u32 pll_con, mdiv, pdiv, sdiv;
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u64 fvco = parent_rate;
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pll_con = readl_relaxed(pll->con_reg);
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mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
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pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
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sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
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fvco *= (2 * (mdiv + 8));
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do_div(fvco, (pdiv + 2) << sdiv);
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return (unsigned int)fvco;
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}
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static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct samsung_clk_pll *pll = to_clk_pll(hw);
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const struct samsung_pll_rate_table *rate;
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u32 tmp;
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/* Get required rate settings from table */
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rate = samsung_get_pll_settings(pll, drate);
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if (!rate) {
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pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
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drate, clk_hw_get_name(hw));
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return -EINVAL;
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}
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tmp = readl_relaxed(pll->con_reg);
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/* Change PLL PMS values */
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tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) |
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(PLLS3C2410_PDIV_MASK << PLLS3C2410_PDIV_SHIFT) |
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(PLLS3C2410_SDIV_MASK << PLLS3C2410_SDIV_SHIFT));
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tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) |
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(rate->pdiv << PLLS3C2410_PDIV_SHIFT) |
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(rate->sdiv << PLLS3C2410_SDIV_SHIFT);
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writel_relaxed(tmp, pll->con_reg);
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/* Time to settle according to the manual */
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udelay(300);
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return 0;
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}
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static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable)
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{
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struct samsung_clk_pll *pll = to_clk_pll(hw);
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u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
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u32 pll_en_orig = pll_en;
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if (enable)
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pll_en &= ~BIT(bit);
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else
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pll_en |= BIT(bit);
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writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
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/* if we started the UPLL, then allow to settle */
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if (enable && (pll_en_orig & BIT(bit)))
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udelay(300);
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return 0;
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}
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static int samsung_s3c2410_mpll_enable(struct clk_hw *hw)
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{
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return samsung_s3c2410_pll_enable(hw, 5, true);
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}
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static void samsung_s3c2410_mpll_disable(struct clk_hw *hw)
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{
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samsung_s3c2410_pll_enable(hw, 5, false);
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}
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static int samsung_s3c2410_upll_enable(struct clk_hw *hw)
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{
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return samsung_s3c2410_pll_enable(hw, 7, true);
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}
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static void samsung_s3c2410_upll_disable(struct clk_hw *hw)
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{
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samsung_s3c2410_pll_enable(hw, 7, false);
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}
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static const struct clk_ops samsung_s3c2410_mpll_clk_min_ops = {
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.recalc_rate = samsung_s3c2410_pll_recalc_rate,
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.enable = samsung_s3c2410_mpll_enable,
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.disable = samsung_s3c2410_mpll_disable,
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};
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static const struct clk_ops samsung_s3c2410_upll_clk_min_ops = {
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.recalc_rate = samsung_s3c2410_pll_recalc_rate,
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.enable = samsung_s3c2410_upll_enable,
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.disable = samsung_s3c2410_upll_disable,
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};
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static const struct clk_ops samsung_s3c2440_mpll_clk_min_ops = {
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.recalc_rate = samsung_s3c2440_mpll_recalc_rate,
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.enable = samsung_s3c2410_mpll_enable,
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.disable = samsung_s3c2410_mpll_disable,
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};
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static const struct clk_ops samsung_s3c2410_mpll_clk_ops = {
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.recalc_rate = samsung_s3c2410_pll_recalc_rate,
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.enable = samsung_s3c2410_mpll_enable,
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.disable = samsung_s3c2410_mpll_disable,
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.round_rate = samsung_pll_round_rate,
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.set_rate = samsung_s3c2410_pll_set_rate,
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};
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static const struct clk_ops samsung_s3c2410_upll_clk_ops = {
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.recalc_rate = samsung_s3c2410_pll_recalc_rate,
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.enable = samsung_s3c2410_upll_enable,
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.disable = samsung_s3c2410_upll_disable,
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.round_rate = samsung_pll_round_rate,
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.set_rate = samsung_s3c2410_pll_set_rate,
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};
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static const struct clk_ops samsung_s3c2440_mpll_clk_ops = {
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.recalc_rate = samsung_s3c2440_mpll_recalc_rate,
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.enable = samsung_s3c2410_mpll_enable,
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.disable = samsung_s3c2410_mpll_disable,
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.round_rate = samsung_pll_round_rate,
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.set_rate = samsung_s3c2410_pll_set_rate,
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};
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/*
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* PLL2550x Clock Type
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*/
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@ -1530,24 +1367,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
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else
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init.ops = &samsung_pll46xx_clk_ops;
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break;
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case pll_s3c2410_mpll:
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if (!pll->rate_table)
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init.ops = &samsung_s3c2410_mpll_clk_min_ops;
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else
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init.ops = &samsung_s3c2410_mpll_clk_ops;
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break;
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case pll_s3c2410_upll:
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if (!pll->rate_table)
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init.ops = &samsung_s3c2410_upll_clk_min_ops;
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else
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init.ops = &samsung_s3c2410_upll_clk_ops;
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break;
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case pll_s3c2440_mpll:
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if (!pll->rate_table)
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init.ops = &samsung_s3c2440_mpll_clk_min_ops;
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else
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init.ops = &samsung_s3c2440_mpll_clk_ops;
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break;
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case pll_2550x:
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init.ops = &samsung_pll2550x_clk_ops;
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break;
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@ -25,9 +25,6 @@ enum samsung_pll_type {
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pll_6552,
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pll_6552_s3c2416,
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pll_6553,
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pll_s3c2410_mpll,
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pll_s3c2410_upll,
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pll_s3c2440_mpll,
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pll_2550x,
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pll_2550xx,
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pll_2650x,
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@ -56,24 +53,6 @@ enum samsung_pll_type {
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.sdiv = (_s), \
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}
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#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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_m + 8, _p + 2, _s, 0, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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}
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#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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2 * (_m + 8), _p + 2, _s, 0, 16), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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}
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#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
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{ \
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.rate = PLL_VALID_RATE(_fin, _rate, \
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