dt-bindings: soc: fsl: cpm_qe: Add TSA controller
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC such as MPC885 or MPC866. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20230217145645.1768659-2-herve.codina@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Herve Codina
Mark Brown
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: PowerQUICC CPM Time-slot assigner (TSA) controller
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maintainers:
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- Herve Codina <herve.codina@bootlin.com>
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description:
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The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
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Its purpose is to route some TDM time-slots to other internal serial
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controllers.
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properties:
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compatible:
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items:
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- enum:
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- fsl,mpc885-tsa
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- fsl,mpc866-tsa
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- const: fsl,cpm1-tsa
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reg:
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items:
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- description: SI (Serial Interface) register base
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- description: SI RAM base
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reg-names:
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items:
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- const: si_regs
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- const: si_ram
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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'#fsl,serial-cells':
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$ref: /schemas/types.yaml#/definitions/uint32
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const: 1
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description:
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TSA consumers that use a phandle to TSA need to pass the serial identifier
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with this phandle (defined in dt-bindings/soc/fsl,tsa.h).
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For instance "fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;".
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patternProperties:
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'^tdm@[0-1]$':
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description:
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The TDM managed by this controller
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type: object
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additionalProperties: false
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properties:
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reg:
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minimum: 0
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maximum: 1
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description:
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The TDM number for this TDM, 0 for TDMa and 1 for TDMb
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fsl,common-rxtx-pins:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
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clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
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Without the 'fsl,common-rxtx-pins' property, the four pins are used.
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With the 'fsl,common-rxtx-pins' property, two pins are used.
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clocks:
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minItems: 2
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items:
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- description: External clock connected to L1RSYNC pin
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- description: External clock connected to L1RCLK pin
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- description: External clock connected to L1TSYNC pin
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- description: External clock connected to L1TCLK pin
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clock-names:
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minItems: 2
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items:
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- const: l1rsync
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- const: l1rclk
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- const: l1tsync
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- const: l1tclk
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fsl,rx-frame-sync-delay-bits:
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enum: [0, 1, 2, 3]
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default: 0
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description: |
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Receive frame sync delay in number of bits.
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Indicates the delay between the Rx sync and the first bit of the Rx
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frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
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fsl,tx-frame-sync-delay-bits:
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enum: [0, 1, 2, 3]
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default: 0
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description: |
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Transmit frame sync delay in number of bits.
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Indicates the delay between the Tx sync and the first bit of the Tx
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frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
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fsl,clock-falling-edge:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Data is sent on falling edge of the clock (and received on the rising
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edge). If 'clock-falling-edge' is not present, data is sent on the
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rising edge (and received on the falling edge).
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fsl,fsync-rising-edge:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Frame sync pulses are sampled with the rising edge of the channel
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clock. If 'fsync-rising-edge' is not present, pulses are sampled with
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the falling edge.
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fsl,double-speed-clock:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The channel clock is twice the data rate.
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patternProperties:
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'^fsl,[rt]x-ts-routes$':
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description: |
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A list of tuple that indicates the Tx or Rx time-slots routes.
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items:
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items:
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- description:
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The number of time-slots
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minimum: 1
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maximum: 64
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- description: |
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The source (Tx) or destination (Rx) serial interface
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(dt-bindings/soc/cpm1-fsl,tsa.h defines these values)
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- 0: No destination
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- 1: SCC2
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- 2: SCC3
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- 3: SCC4
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- 4: SMC1
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- 5: SMC2
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enum: [0, 1, 2, 3, 4, 5]
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minItems: 1
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maxItems: 64
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allOf:
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# If fsl,common-rxtx-pins is present, only 2 clocks are needed.
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# Else, the 4 clocks must be present.
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- if:
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required:
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- fsl,common-rxtx-pins
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then:
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properties:
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clocks:
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maxItems: 2
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clock-names:
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maxItems: 2
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else:
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properties:
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clocks:
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minItems: 4
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clock-names:
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minItems: 4
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required:
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- reg
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- clocks
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- clock-names
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required:
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- compatible
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- reg
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- reg-names
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- '#address-cells'
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- '#size-cells'
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- '#fsl,serial-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/soc/cpm1-fsl,tsa.h>
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tsa@ae0 {
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compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
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reg = <0xae0 0x10>,
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<0xc00 0x200>;
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reg-names = "si_regs", "si_ram";
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#address-cells = <1>;
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#size-cells = <0>;
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#fsl,serial-cells = <1>;
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tdm@0 {
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/* TDMa */
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reg = <0>;
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clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
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clock-names = "l1rsync", "l1rclk";
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fsl,common-rxtx-pins;
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fsl,fsync-rising-edge;
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fsl,tx-ts-routes = <2 0>, /* TS 0..1 */
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<24 FSL_CPM_TSA_SCC4>, /* TS 2..25 */
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<1 0>, /* TS 26 */
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<5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */
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fsl,rx-ts-routes = <2 0>, /* TS 0..1 */
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<24 FSL_CPM_TSA_SCC4>, /* 2..25 */
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<1 0>, /* TS 26 */
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<5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */
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};
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};
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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#ifndef __DT_BINDINGS_SOC_FSL_TSA_H
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#define __DT_BINDINGS_SOC_FSL_TSA_H
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#define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */
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#define FSL_CPM_TSA_SCC2 1
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#define FSL_CPM_TSA_SCC3 2
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#define FSL_CPM_TSA_SCC4 3
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#define FSL_CPM_TSA_SMC1 4
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#define FSL_CPM_TSA_SMC2 5
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#endif
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