OrgACRN
/
acrn-kernel
mirror of https://github.com/projectacrn/acrn-kernel.git
1
0
Fork 0
Code Issues Releases Wiki Activity

sh: Avoid using IRQ0 on SH3 and SH4 

[ Upstream commit a8ac296114 ]

IRQ0 is no longer returned by platform_get_irq() and its ilk -- they now
return -EINVAL instead.  However, the kernel code supporting SH3/4-based
SoCs still maps the IRQ #s starting at 0 -- modify that code to start the
IRQ #s from 16 instead.

The patch should mostly affect the AP-SH4A-3A/AP-SH4AD-0A boards as they
indeed are using IRQ0 for the SMSC911x compatible Ethernet chip.

Fixes: ce753ad154 ("platform: finally disallow IRQ0 in platform_get_irq() and its ilk")
Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Tested-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Link: https://lore.kernel.org/r/71105dbf-cdb0-72e1-f9eb-eeda8e321696@omp.ru
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Sergey Shtylyov 2023-06-01 23:22:17 +03:00 committed by Greg Kroah-Hartman
parent d199218881
commit f5d7f9e155
6 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/sh/include/mach-common/mach/highlander.h
View File

@ -176,7 +176,7 @@
#define IVDR_CK_ON 4 /* iVDR Clock ON */ #define IVDR_CK_ON 4 /* iVDR Clock ON */
#endif #endif
#define HL_FPGA_IRQ_BASE 200 #define HL_FPGA_IRQ_BASE (200 + 16)
#define HL_NR_IRL 15 #define HL_NR_IRL 15
#define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0) #define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0)

2
arch/sh/include/mach-common/mach/r2d.h
View File

@ -47,7 +47,7 @@
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
#define R2D_FPGA_IRQ_BASE 100 #define R2D_FPGA_IRQ_BASE (100 + 16)
#define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0) #define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0)
#define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1) #define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1)

2
arch/sh/include/mach-dreamcast/mach/sysasic.h
View File

@ -22,7 +22,7 @@
takes. takes.
*/ */
#define HW_EVENT_IRQ_BASE 48 #define HW_EVENT_IRQ_BASE (48 + 16)
/* IRQ 13 */ /* IRQ 13 */
#define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */ #define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */

2
arch/sh/include/mach-se/mach/se7724.h
View File

@ -37,7 +37,7 @@
#define IRQ2_IRQ evt2irq(0x640) #define IRQ2_IRQ evt2irq(0x640)
/* Bits in IRQ012 registers */ /* Bits in IRQ012 registers */
#define SE7724_FPGA_IRQ_BASE 220 #define SE7724_FPGA_IRQ_BASE (220 + 16)
/* IRQ0 */ /* IRQ0 */
#define IRQ0_BASE SE7724_FPGA_IRQ_BASE #define IRQ0_BASE SE7724_FPGA_IRQ_BASE

4
arch/sh/kernel/cpu/sh3/entry.S
View File

@ -470,9 +470,9 @@ ENTRY(handle_interrupt)
mov r4, r0 ! save vector->jmp table offset for later mov r4, r0 ! save vector->jmp table offset for later
shlr2 r4 ! vector to IRQ# conversion shlr2 r4 ! vector to IRQ# conversion
add #-0x10, r4
cmp/pz r4 ! is it a valid IRQ? mov #0x10, r5
cmp/hs r5, r4 ! is it a valid IRQ?
bt 10f bt 10f
/* /*

6
include/linux/sh_intc.h
View File

@ -13,9 +13,9 @@
/* /*
* Convert back and forth between INTEVT and IRQ values. * Convert back and forth between INTEVT and IRQ values.
*/ */
#ifdef CONFIG_CPU_HAS_INTEVT #ifdef CONFIG_CPU_HAS_INTEVT /* Avoid IRQ0 (invalid for platform devices) */
#define evt2irq(evt) (((evt) >> 5) - 16) #define evt2irq(evt) ((evt) >> 5)
#define irq2evt(irq) (((irq) + 16) << 5) #define irq2evt(irq) ((irq) << 5)
#else #else
#define evt2irq(evt) (evt) #define evt2irq(evt) (evt)
#define irq2evt(irq) (irq) #define irq2evt(irq) (irq)